/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* pcicfg.h: PCI configuration constants and structures.
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: pcicfg.h 621340 2016-02-25 12:26:40Z $
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*/
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#ifndef _h_pcicfg_
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#define _h_pcicfg_
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/* pci config status reg has a bit to indicate that capability ptr is present */
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#define PCI_CAPPTR_PRESENT 0x0010
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/* A structure for the config registers is nice, but in most
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* systems the config space is not memory mapped, so we need
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* field offsetts. :-(
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*/
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#define PCI_CFG_VID 0
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#define PCI_CFG_DID 2
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#define PCI_CFG_CMD 4
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#define PCI_CFG_STAT 6
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#define PCI_CFG_REV 8
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#define PCI_CFG_PROGIF 9
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#define PCI_CFG_SUBCL 0xa
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#define PCI_CFG_BASECL 0xb
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#define PCI_CFG_CLSZ 0xc
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#define PCI_CFG_LATTIM 0xd
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#define PCI_CFG_HDR 0xe
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#define PCI_CFG_BIST 0xf
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#define PCI_CFG_BAR0 0x10
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/*
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* TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be
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* 0x18 as per the PCIe full dongle spec. Need to modify the values below
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* correctly at a later point of time
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*/
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#ifdef DHD_EFI
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#define PCI_CFG_BAR1 0x18
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#else
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#define PCI_CFG_BAR1 0x14
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#endif /* DHD_EFI */
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#define PCI_CFG_BAR2 0x18
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#define PCI_CFG_BAR3 0x1c
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#define PCI_CFG_BAR4 0x20
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#define PCI_CFG_BAR5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SVID 0x2c
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#define PCI_CFG_SSID 0x2e
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#define PCI_CFG_ROMBAR 0x30
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#define PCI_CFG_CAPPTR 0x34
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#define PCI_CFG_INT 0x3c
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#define PCI_CFG_PIN 0x3d
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#define PCI_CFG_MINGNT 0x3e
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#define PCI_CFG_MAXLAT 0x3f
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#define PCI_CFG_DEVCTRL 0xd8
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#define PCI_CFG_TLCNTRL_5 0x814
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/* PCI CAPABILITY DEFINES */
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#define PCI_CAP_POWERMGMTCAP_ID 0x01
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#define PCI_CAP_MSICAP_ID 0x05
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#define PCI_CAP_VENDSPEC_ID 0x09
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#define PCI_CAP_PCIECAP_ID 0x10
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/* Data structure to define the Message Signalled Interrupt facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_msi {
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uint8 capID;
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uint8 nextptr;
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uint16 msgctrl;
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uint32 msgaddr;
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} pciconfig_cap_msi;
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#define MSI_ENABLE 0x1 /* bit 0 of msgctrl */
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/* Data structure to define the Power managment facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_pwrmgmt {
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uint8 capID;
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uint8 nextptr;
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uint16 pme_cap;
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uint16 pme_sts_ctrl;
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uint8 pme_bridge_ext;
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uint8 data;
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} pciconfig_cap_pwrmgmt;
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#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
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#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
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#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
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#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
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/* Data structure to define the PCIE capability */
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typedef struct _pciconfig_cap_pcie {
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uint8 capID;
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uint8 nextptr;
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uint16 pcie_cap;
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uint32 dev_cap;
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uint16 dev_ctrl;
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uint16 dev_status;
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uint32 link_cap;
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uint16 link_ctrl;
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uint16 link_status;
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uint32 slot_cap;
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uint16 slot_ctrl;
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uint16 slot_status;
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uint16 root_ctrl;
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uint16 root_cap;
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uint32 root_status;
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} pciconfig_cap_pcie;
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/* PCIE Enhanced CAPABILITY DEFINES */
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#define PCIE_EXTCFG_OFFSET 0x100
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#define PCIE_ADVERRREP_CAPID 0x0001
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#define PCIE_VC_CAPID 0x0002
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#define PCIE_DEVSNUM_CAPID 0x0003
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#define PCIE_PWRBUDGET_CAPID 0x0004
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/* PCIE Extended configuration */
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#define PCIE_ADV_CORR_ERR_MASK 0x114
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#define CORR_ERR_RE (1 << 0) /* Receiver */
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#define CORR_ERR_BT (1 << 6) /* Bad TLP */
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#define CORR_ERR_BD (1 << 7) /* Bad DLLP */
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#define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
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#define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
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#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
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CORR_ERR_RR | CORR_ERR_RT)
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/* PCIE Root Control Register bits (Host mode only) */
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#define PCIE_RC_CORR_SERR_EN 0x0001
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#define PCIE_RC_NONFATAL_SERR_EN 0x0002
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#define PCIE_RC_FATAL_SERR_EN 0x0004
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#define PCIE_RC_PME_INT_EN 0x0008
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#define PCIE_RC_CRS_EN 0x0010
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/* PCIE Root Capability Register bits (Host mode only) */
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#define PCIE_RC_CRS_VISIBILITY 0x0001
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/* Header to define the PCIE specific capabilities in the extended config space */
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typedef struct _pcie_enhanced_caphdr {
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uint16 capID;
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uint16 cap_ver : 4;
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uint16 next_ptr : 12;
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} pcie_enhanced_caphdr;
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#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
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#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
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#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
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#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
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#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
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#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
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#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
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#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
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#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
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#define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */
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#define PCIE_DC_AER_CORR_EN (1u << 0u)
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#define PCIE_DC_AER_NON_FATAL_EN (1u << 1u)
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#define PCIE_DC_AER_FATAL_EN (1u << 2u)
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#define PCIE_DC_AER_UNSUP_EN (1u << 3u)
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#define PCI_BAR0_WIN2_OFFSET 0x1000u
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#define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u
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#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
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#define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */
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/* Private Registers */
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#define PCI_STAT_CTRL 0xa80
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#define PCI_L0_EVENTCNT 0xa84
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#define PCI_L0_STATETMR 0xa88
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#define PCI_L1_EVENTCNT 0xa8c
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#define PCI_L1_STATETMR 0xa90
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#define PCI_L1_1_EVENTCNT 0xa94
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#define PCI_L1_1_STATETMR 0xa98
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#define PCI_L1_2_EVENTCNT 0xa9c
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#define PCI_L1_2_STATETMR 0xaa0
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#define PCI_L2_EVENTCNT 0xaa4
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#define PCI_L2_STATETMR 0xaa8
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#define PCI_LINK_STATUS 0x4dc
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#define PCI_LINK_SPEED_MASK (15u << 0u)
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#define PCI_LINK_SPEED_SHIFT (0)
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#define PCIE_LNK_SPEED_GEN1 0x1
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#define PCIE_LNK_SPEED_GEN2 0x2
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#define PCIE_LNK_SPEED_GEN3 0x3
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#define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */
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#define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u)
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#define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31)
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#define PCI_PMCR_REFUP 0x1814 /* Trefup time */
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#define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */
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#define PCI_TPOWER_SCALE_MASK 0x3
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#define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
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#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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/*
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* PCIE GEN2 changed some of the above locations for
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* Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase
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* BAR0 maps 32K of register space
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*/
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#define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */
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#define PCI_BAR0_WIN2_OFFSET 0x1000u
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#define PCI_CORE_ENUM_OFFSET 0x2000u
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#define PCI_CC_CORE_ENUM_OFFSET 0x3000u
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#define PCI_SEC_BAR0_WIN_OFFSET 0x4000u
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#define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u
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#define PCI_CORE_ENUM2_OFFSET 0x6000u
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#define PCI_CC_CORE_ENUM2_OFFSET 0x7000u
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#define PCI_LAST_OFFSET 0x8000u
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#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
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#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
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#define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */
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/* On AI chips we have a second window to map DMP regs are mapped: */
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#define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
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/* PCI_INT_STATUS */
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#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
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/* PCI_INT_MASK */
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#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
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#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
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#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
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#define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */
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#define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */
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/* PCI_SPROM_CONTROL */
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#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
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#define SPROM_LOCKED 0x08 /* SPROM Locked */
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#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
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#define SPROM_WRITEEN 0x10 /* SPROM write enable */
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#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
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#define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
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#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
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#define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */
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/* Bits in PCI command and status regs */
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#define PCI_CMD_IO 0x00000001 /* I/O enable */
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#define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
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#define PCI_CMD_MASTER 0x00000004 /* Master enable */
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#define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
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#define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
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#define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
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#define PCI_STAT_TA 0x08000000 /* target abort status */
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/* Header types */
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#define PCI_HEADER_MULTI 0x80
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#define PCI_HEADER_MASK 0x7f
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typedef enum {
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PCI_HEADER_NORMAL,
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PCI_HEADER_BRIDGE,
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PCI_HEADER_CARDBUS
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} pci_header_types;
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#define PCI_CONFIG_SPACE_SIZE 256
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#define DWORD_ALIGN(x) (x & ~(0x03))
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#define BYTE_POS(x) (x & 0x3)
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#define WORD_POS(x) (x & 0x1)
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#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
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#define WORD_SHIFT(x) (16 * WORD_POS(x))
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#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
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#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
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#define read_pci_cfg_byte(a) \
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(BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff)
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#define read_pci_cfg_word(a) \
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(WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
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#define write_pci_cfg_byte(a, val) do { \
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uint32 tmpval; \
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tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
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val << BYTE_POS(a); \
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OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
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} while (0)
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#define write_pci_cfg_word(a, val) do { \
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uint32 tmpval; \
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tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
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val << WORD_POS(a); \
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OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
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} while (0)
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#endif /* _h_pcicfg_ */
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