/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef B43_PHY_AC_H_
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#define B43_PHY_AC_H_
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#include "phy_common.h"
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#define B43_PHY_AC_BBCFG 0x001
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#define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
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#define B43_PHY_AC_BANDCTL 0x003 /* Band control */
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#define B43_PHY_AC_BANDCTL_5GHZ 0x0001
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#define B43_PHY_AC_TABLE_ID 0x00d
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#define B43_PHY_AC_TABLE_OFFSET 0x00e
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#define B43_PHY_AC_TABLE_DATA1 0x00f
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#define B43_PHY_AC_TABLE_DATA2 0x010
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#define B43_PHY_AC_TABLE_DATA3 0x011
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#define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
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#define B43_PHY_AC_CLASSCTL_CCKEN 0x0001 /* CCK enable */
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#define B43_PHY_AC_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */
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#define B43_PHY_AC_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */
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#define B43_PHY_AC_BW1A 0x371
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#define B43_PHY_AC_BW2 0x372
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#define B43_PHY_AC_BW3 0x373
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#define B43_PHY_AC_BW4 0x374
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#define B43_PHY_AC_BW5 0x375
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#define B43_PHY_AC_BW6 0x376
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#define B43_PHY_AC_RFCTL_CMD 0x408
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#define B43_PHY_AC_C1_CLIP 0x6d4
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#define B43_PHY_AC_C1_CLIP_DIS 0x4000
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#define B43_PHY_AC_C2_CLIP 0x8d4
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#define B43_PHY_AC_C2_CLIP_DIS 0x4000
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#define B43_PHY_AC_C3_CLIP 0xad4
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#define B43_PHY_AC_C3_CLIP_DIS 0x4000
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struct b43_phy_ac {
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};
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extern const struct b43_phy_operations b43_phyops_ac;
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#endif /* B43_PHY_AC_H_ */
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