/*
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* Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TXRX_H_
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#define _TXRX_H_
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#include <linux/etherdevice.h>
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#include "wcn36xx.h"
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/* TODO describe all properties */
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#define WCN36XX_802_11_HEADER_LEN 24
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#define WCN36XX_BMU_WQ_TX 25
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#define WCN36XX_TID 7
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/* broadcast wq ID */
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#define WCN36XX_TX_B_WQ_ID 0xA
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#define WCN36XX_TX_U_WQ_ID 0x9
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/* bd_rate */
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#define WCN36XX_BD_RATE_DATA 0
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#define WCN36XX_BD_RATE_MGMT 2
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#define WCN36XX_BD_RATE_CTRL 3
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enum wcn36xx_txbd_ssn_type {
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WCN36XX_TXBD_SSN_FILL_HOST = 0,
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WCN36XX_TXBD_SSN_FILL_DPU_NON_QOS = 1,
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WCN36XX_TXBD_SSN_FILL_DPU_QOS = 2,
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};
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struct wcn36xx_pdu {
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u32 dpu_fb:8;
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u32 adu_fb:8;
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u32 pdu_id:16;
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/* 0x04*/
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u32 tail_pdu_idx:16;
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u32 head_pdu_idx:16;
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/* 0x08*/
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u32 pdu_count:7;
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u32 mpdu_data_off:9;
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u32 mpdu_header_off:8;
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u32 mpdu_header_len:8;
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/* 0x0c*/
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u32 reserved4:8;
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u32 tid:4;
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u32 bd_ssn:2;
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u32 reserved3:2;
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u32 mpdu_len:16;
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};
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struct wcn36xx_rx_bd {
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u32 bdt:2;
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u32 ft:1;
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u32 dpu_ne:1;
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u32 rx_key_id:3;
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u32 ub:1;
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u32 rmf:1;
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u32 uma_bypass:1;
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u32 csr11:1;
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u32 reserved0:1;
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u32 scan_learn:1;
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u32 rx_ch:4;
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u32 rtsf:1;
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u32 bsf:1;
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u32 a2hf:1;
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u32 st_auf:1;
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u32 dpu_sign:3;
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u32 dpu_rf:8;
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struct wcn36xx_pdu pdu;
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/* 0x14*/
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u32 addr3:8;
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u32 addr2:8;
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u32 addr1:8;
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u32 dpu_desc_idx:8;
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/* 0x18*/
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u32 rxp_flags:23;
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u32 rate_id:9;
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u32 phy_stat0;
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u32 phy_stat1;
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/* 0x24 */
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u32 rx_times;
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u32 pmi_cmd[6];
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/* 0x40 */
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u32 reserved7:4;
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u32 reorder_slot_id:6;
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u32 reorder_fwd_id:6;
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u32 reserved6:12;
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u32 reorder_code:4;
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/* 0x44 */
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u32 exp_seq_num:12;
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u32 cur_seq_num:12;
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u32 rf_band:2;
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u32 fr_type_subtype:6;
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/* 0x48 */
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u32 msdu_size:16;
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u32 sub_fr_id:4;
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u32 proc_order:4;
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u32 reserved9:4;
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u32 aef:1;
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u32 lsf:1;
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u32 esf:1;
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u32 asf:1;
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};
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struct wcn36xx_tx_bd {
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u32 bdt:2;
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u32 ft:1;
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u32 dpu_ne:1;
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u32 fw_tx_comp:1;
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u32 tx_comp:1;
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u32 reserved1:1;
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u32 ub:1;
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u32 rmf:1;
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u32 reserved0:12;
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u32 dpu_sign:3;
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u32 dpu_rf:8;
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struct wcn36xx_pdu pdu;
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/* 0x14*/
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u32 reserved5:7;
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u32 queue_id:5;
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u32 bd_rate:2;
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u32 ack_policy:2;
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u32 sta_index:8;
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u32 dpu_desc_idx:8;
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u32 tx_bd_sign;
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u32 reserved6;
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u32 dxe_start_time;
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u32 dxe_end_time;
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/*u32 tcp_udp_start_off:10;
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u32 header_cks:16;
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u32 reserved7:6;*/
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};
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struct wcn36xx_sta;
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struct wcn36xx;
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int wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb);
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int wcn36xx_start_tx(struct wcn36xx *wcn,
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struct wcn36xx_sta *sta_priv,
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struct sk_buff *skb);
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#endif /* _TXRX_H_ */
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