/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
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* Ethernet MAC Sliver (CPGMAC_SL) APIs
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*
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* Copyright (C) 2019 Texas Instruments
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*
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*/
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#ifndef __TI_CPSW_SL_H__
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#define __TI_CPSW_SL_H__
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#include <linux/device.h>
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enum cpsw_sl_regs {
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CPSW_SL_IDVER,
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CPSW_SL_MACCONTROL,
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CPSW_SL_MACSTATUS,
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CPSW_SL_SOFT_RESET,
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CPSW_SL_RX_MAXLEN,
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CPSW_SL_BOFFTEST,
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CPSW_SL_RX_PAUSE,
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CPSW_SL_TX_PAUSE,
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CPSW_SL_EMCONTROL,
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CPSW_SL_RX_PRI_MAP,
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CPSW_SL_TX_GAP,
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};
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enum {
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CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
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CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
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CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
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CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
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CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
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CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
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CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
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CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
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CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */
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CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */
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CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */
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CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */
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CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */
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CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */
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CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */
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CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */
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CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */
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CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
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CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
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CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */
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CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */
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CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */
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CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */
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CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */
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CPSW_SL_CTL_FUNCS_COUNT
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};
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struct cpsw_sl;
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struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
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void __iomem *sl_base);
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void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo);
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u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs);
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u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs);
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void cpsw_sl_ctl_reset(struct cpsw_sl *sl);
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int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo);
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u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg);
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void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val);
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#endif /* __TI_CPSW_SL_H__ */
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