/* SPDX-License-Identifier: GPL-2.0-only */
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/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*/
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#ifndef __SXGBE_DMA_H__
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#define __SXGBE_DMA_H__
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/* forward declaration */
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struct sxgbe_extra_stats;
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#define SXGBE_DMA_BLENMAP_LSHIFT 1
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#define SXGBE_DMA_TXPBL_LSHIFT 16
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#define SXGBE_DMA_RXPBL_LSHIFT 16
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#define DEFAULT_DMA_PBL 8
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struct sxgbe_dma_ops {
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/* DMA core initialization */
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int (*init)(void __iomem *ioaddr, int fix_burst, int burst_map);
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void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst,
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int pbl, dma_addr_t dma_tx, dma_addr_t dma_rx,
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int t_rzie, int r_rsize);
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void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum);
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void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum);
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void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum);
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void (*start_tx)(void __iomem *ioaddr, int tchannels);
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void (*start_tx_queue)(void __iomem *ioaddr, int dma_cnum);
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void (*stop_tx)(void __iomem *ioaddr, int tchannels);
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void (*stop_tx_queue)(void __iomem *ioaddr, int dma_cnum);
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void (*start_rx)(void __iomem *ioaddr, int rchannels);
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void (*stop_rx)(void __iomem *ioaddr, int rchannels);
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int (*tx_dma_int_status)(void __iomem *ioaddr, int channel_no,
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struct sxgbe_extra_stats *x);
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int (*rx_dma_int_status)(void __iomem *ioaddr, int channel_no,
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struct sxgbe_extra_stats *x);
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/* Program the HW RX Watchdog */
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void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt);
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/* Enable TSO for each DMA channel */
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void (*enable_tso)(void __iomem *ioaddr, u8 chan_num);
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};
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const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void);
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#endif /* __SXGBE_CORE_H__ */
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