// SPDX-License-Identifier: GPL-2.0-only
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/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include "sxgbe_common.h"
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#include "sxgbe_reg.h"
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/* MAC core initialization */
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static void sxgbe_core_init(void __iomem *ioaddr)
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{
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u32 regval;
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/* TX configuration */
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regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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/* Other configurable parameters IFP, IPG, ISR, ISM
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* needs to be set if needed
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*/
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regval |= SXGBE_TX_JABBER_DISABLE;
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writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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/* RX configuration */
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regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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/* Other configurable parameters CST, SPEN, USP, GPSLCE
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* WD, LM, S2KP, HDSMS, GPSL, ELEN, ARPEN needs to be
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* set if needed
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*/
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regval |= SXGBE_RX_JUMBPKT_ENABLE | SXGBE_RX_ACS_ENABLE;
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writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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/* Dump MAC registers */
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static void sxgbe_core_dump_regs(void __iomem *ioaddr)
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{
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}
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static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status)
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{
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int status = 0;
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int lpi_status;
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/* Reading this register shall clear all the LPI status bits */
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lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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if (lpi_status & LPI_CTRL_STATUS_TLPIEN)
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status |= TX_ENTRY_LPI_MODE;
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if (lpi_status & LPI_CTRL_STATUS_TLPIEX)
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status |= TX_EXIT_LPI_MODE;
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if (lpi_status & LPI_CTRL_STATUS_RLPIEN)
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status |= RX_ENTRY_LPI_MODE;
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if (lpi_status & LPI_CTRL_STATUS_RLPIEX)
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status |= RX_EXIT_LPI_MODE;
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return status;
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}
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/* Handle extra events on specific interrupts hw dependent */
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static int sxgbe_core_host_irq_status(void __iomem *ioaddr,
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struct sxgbe_extra_stats *x)
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{
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int irq_status, status = 0;
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irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG);
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if (unlikely(irq_status & LPI_INT_STATUS))
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status |= sxgbe_get_lpi_status(ioaddr, irq_status);
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return status;
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}
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/* Set power management mode (e.g. magic frame) */
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static void sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode)
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{
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}
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/* Set/Get Unicast MAC addresses */
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static void sxgbe_core_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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u32 high_word, low_word;
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high_word = (addr[5] << 8) | (addr[4]);
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low_word = (addr[3] << 24) | (addr[2] << 16) |
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(addr[1] << 8) | (addr[0]);
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writel(high_word, ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n));
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writel(low_word, ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n));
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}
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static void sxgbe_core_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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u32 high_word, low_word;
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high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n));
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low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n));
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/* extract and assign address */
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addr[5] = (high_word & 0x0000FF00) >> 8;
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addr[4] = (high_word & 0x000000FF);
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addr[3] = (low_word & 0xFF000000) >> 24;
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addr[2] = (low_word & 0x00FF0000) >> 16;
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addr[1] = (low_word & 0x0000FF00) >> 8;
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addr[0] = (low_word & 0x000000FF);
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}
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static void sxgbe_enable_tx(void __iomem *ioaddr, bool enable)
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{
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u32 tx_config;
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tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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tx_config &= ~SXGBE_TX_ENABLE;
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if (enable)
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tx_config |= SXGBE_TX_ENABLE;
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writel(tx_config, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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}
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static void sxgbe_enable_rx(void __iomem *ioaddr, bool enable)
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{
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u32 rx_config;
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rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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rx_config &= ~SXGBE_RX_ENABLE;
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if (enable)
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rx_config |= SXGBE_RX_ENABLE;
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writel(rx_config, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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static int sxgbe_get_controller_version(void __iomem *ioaddr)
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{
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return readl(ioaddr + SXGBE_CORE_VERSION_REG);
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}
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/* If supported then get the optional core features */
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static unsigned int sxgbe_get_hw_feature(void __iomem *ioaddr,
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unsigned char feature_index)
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{
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return readl(ioaddr + (SXGBE_CORE_HW_FEA_REG(feature_index)));
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}
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static void sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed)
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{
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u32 tx_cfg = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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/* clear the speed bits */
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tx_cfg &= ~0x60000000;
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tx_cfg |= (speed << SXGBE_SPEED_LSHIFT);
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/* set the speed */
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writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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}
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static void sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
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reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
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reg_val |= SXGBE_CORE_RXQ_ENABLE;
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writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
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}
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static void sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num)
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{
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u32 reg_val;
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reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
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reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
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reg_val |= SXGBE_CORE_RXQ_DISABLE;
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writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
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}
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static void sxgbe_set_eee_mode(void __iomem *ioaddr)
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{
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u32 ctrl;
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/* Enable the LPI mode for transmit path with Tx automate bit set.
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* When Tx Automate bit is set, MAC internally handles the entry
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* to LPI mode after all outstanding and pending packets are
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* transmitted.
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*/
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ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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ctrl |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA;
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writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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}
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static void sxgbe_reset_eee_mode(void __iomem *ioaddr)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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ctrl &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA);
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writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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}
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static void sxgbe_set_eee_pls(void __iomem *ioaddr, const int link)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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/* If the PHY link status is UP then set PLS */
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if (link)
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ctrl |= LPI_CTRL_STATUS_PLS;
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else
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ctrl &= ~LPI_CTRL_STATUS_PLS;
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writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
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}
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static void sxgbe_set_eee_timer(void __iomem *ioaddr,
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const int ls, const int tw)
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{
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int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
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/* Program the timers in the LPI timer control register:
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* LS: minimum time (ms) for which the link
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* status from PHY should be ok before transmitting
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* the LPI pattern.
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* TW: minimum time (us) for which the core waits
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* after it has stopped transmitting the LPI pattern.
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*/
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writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL);
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}
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static void sxgbe_enable_rx_csum(void __iomem *ioaddr)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE;
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writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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static void sxgbe_disable_rx_csum(void __iomem *ioaddr)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE;
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writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
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}
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static const struct sxgbe_core_ops core_ops = {
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.core_init = sxgbe_core_init,
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.dump_regs = sxgbe_core_dump_regs,
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.host_irq_status = sxgbe_core_host_irq_status,
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.pmt = sxgbe_core_pmt,
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.set_umac_addr = sxgbe_core_set_umac_addr,
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.get_umac_addr = sxgbe_core_get_umac_addr,
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.enable_rx = sxgbe_enable_rx,
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.enable_tx = sxgbe_enable_tx,
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.get_controller_version = sxgbe_get_controller_version,
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.get_hw_feature = sxgbe_get_hw_feature,
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.set_speed = sxgbe_core_set_speed,
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.set_eee_mode = sxgbe_set_eee_mode,
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.reset_eee_mode = sxgbe_reset_eee_mode,
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.set_eee_timer = sxgbe_set_eee_timer,
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.set_eee_pls = sxgbe_set_eee_pls,
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.enable_rx_csum = sxgbe_enable_rx_csum,
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.disable_rx_csum = sxgbe_disable_rx_csum,
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.enable_rxqueue = sxgbe_core_enable_rxqueue,
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.disable_rxqueue = sxgbe_core_disable_rxqueue,
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};
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const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
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{
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return &core_ops;
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}
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