// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*/
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/* Qualcomm Technologies, Inc. FSM9900 EMAC SGMII Controller driver.
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*/
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#include <linux/iopoll.h>
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#include "emac.h"
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/* EMAC_QSERDES register offsets */
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#define EMAC_QSERDES_COM_SYS_CLK_CTRL 0x0000
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#define EMAC_QSERDES_COM_PLL_CNTRL 0x0014
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#define EMAC_QSERDES_COM_PLL_IP_SETI 0x0018
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#define EMAC_QSERDES_COM_PLL_CP_SETI 0x0024
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#define EMAC_QSERDES_COM_PLL_IP_SETP 0x0028
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#define EMAC_QSERDES_COM_PLL_CP_SETP 0x002c
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#define EMAC_QSERDES_COM_SYSCLK_EN_SEL 0x0038
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#define EMAC_QSERDES_COM_RESETSM_CNTRL 0x0040
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#define EMAC_QSERDES_COM_PLLLOCK_CMP1 0x0044
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#define EMAC_QSERDES_COM_PLLLOCK_CMP2 0x0048
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#define EMAC_QSERDES_COM_PLLLOCK_CMP3 0x004c
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#define EMAC_QSERDES_COM_PLLLOCK_CMP_EN 0x0050
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#define EMAC_QSERDES_COM_DEC_START1 0x0064
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#define EMAC_QSERDES_COM_DIV_FRAC_START1 0x0098
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#define EMAC_QSERDES_COM_DIV_FRAC_START2 0x009c
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#define EMAC_QSERDES_COM_DIV_FRAC_START3 0x00a0
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#define EMAC_QSERDES_COM_DEC_START2 0x00a4
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#define EMAC_QSERDES_COM_PLL_CRCTRL 0x00ac
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#define EMAC_QSERDES_COM_RESET_SM 0x00bc
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#define EMAC_QSERDES_TX_BIST_MODE_LANENO 0x0100
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#define EMAC_QSERDES_TX_TX_EMP_POST1_LVL 0x0108
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#define EMAC_QSERDES_TX_TX_DRV_LVL 0x010c
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#define EMAC_QSERDES_TX_LANE_MODE 0x0150
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#define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN 0x0170
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#define EMAC_QSERDES_RX_CDR_CONTROL 0x0200
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#define EMAC_QSERDES_RX_CDR_CONTROL2 0x0210
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#define EMAC_QSERDES_RX_RX_EQ_GAIN12 0x0230
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/* EMAC_SGMII register offsets */
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#define EMAC_SGMII_PHY_SERDES_START 0x0000
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#define EMAC_SGMII_PHY_CMN_PWR_CTRL 0x0004
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#define EMAC_SGMII_PHY_RX_PWR_CTRL 0x0008
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#define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
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#define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
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#define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
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#define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
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#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
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#define PLL_IPSETI(x) ((x) & 0x3f)
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#define PLL_CPSETI(x) ((x) & 0xff)
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#define PLL_IPSETP(x) ((x) & 0x3f)
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#define PLL_CPSETP(x) ((x) & 0x1f)
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#define PLL_RCTRL(x) (((x) & 0xf) << 4)
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#define PLL_CCTRL(x) ((x) & 0xf)
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#define LANE_MODE(x) ((x) & 0x1f)
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#define SYSCLK_CM BIT(4)
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#define SYSCLK_AC_COUPLE BIT(3)
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#define OCP_EN BIT(5)
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#define PLL_DIV_FFEN BIT(2)
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#define PLL_DIV_ORD BIT(1)
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#define SYSCLK_SEL_CMOS BIT(3)
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#define FRQ_TUNE_MODE BIT(4)
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#define PLLLOCK_CMP_EN BIT(0)
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#define DEC_START1_MUX BIT(7)
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#define DEC_START1(x) ((x) & 0x7f)
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#define DIV_FRAC_START_MUX BIT(7)
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#define DIV_FRAC_START(x) ((x) & 0x7f)
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#define DIV_FRAC_START3_MUX BIT(4)
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#define DIV_FRAC_START3(x) ((x) & 0xf)
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#define DEC_START2_MUX BIT(1)
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#define DEC_START2 BIT(0)
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#define READY BIT(5)
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#define TX_EMP_POST1_LVL_MUX BIT(5)
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#define TX_EMP_POST1_LVL(x) ((x) & 0x1f)
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#define TX_DRV_LVL_MUX BIT(4)
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#define TX_DRV_LVL(x) ((x) & 0xf)
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#define EMP_EN_MUX BIT(1)
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#define EMP_EN BIT(0)
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#define SECONDORDERENABLE BIT(6)
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#define FIRSTORDER_THRESH(x) (((x) & 0x7) << 3)
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#define SECONDORDERGAIN(x) ((x) & 0x7)
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#define RX_EQ_GAIN2(x) (((x) & 0xf) << 4)
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#define RX_EQ_GAIN1(x) ((x) & 0xf)
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#define SERDES_START BIT(0)
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#define BIAS_EN BIT(6)
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#define PLL_EN BIT(5)
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#define SYSCLK_EN BIT(4)
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#define CLKBUF_L_EN BIT(3)
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#define PLL_TXCLK_EN BIT(1)
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#define PLL_RXCLK_EN BIT(0)
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#define L0_RX_SIGDET_EN BIT(7)
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#define L0_RX_TERM_MODE(x) (((x) & 3) << 4)
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#define L0_RX_I_EN BIT(1)
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#define L0_TX_EN BIT(5)
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#define L0_CLKBUF_EN BIT(4)
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#define L0_TRAN_BIAS_EN BIT(1)
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#define L0_RX_EQUALIZE_ENABLE BIT(6)
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#define L0_RESET_TSYNC_EN BIT(4)
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#define L0_DRV_LVL(x) ((x) & 0xf)
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#define PWRDN_B BIT(0)
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#define CDR_MAX_CNT(x) ((x) & 0xff)
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#define PLLLOCK_CMP(x) ((x) & 0xff)
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#define SERDES_START_WAIT_TIMES 100
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struct emac_reg_write {
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unsigned int offset;
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u32 val;
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};
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static void emac_reg_write_all(void __iomem *base,
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const struct emac_reg_write *itr, size_t size)
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{
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size_t i;
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for (i = 0; i < size; ++itr, ++i)
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writel(itr->val, base + itr->offset);
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}
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static const struct emac_reg_write physical_coding_sublayer_programming[] = {
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{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
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{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL,
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BIAS_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
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{EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN | L0_TRAN_BIAS_EN},
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{EMAC_SGMII_PHY_RX_PWR_CTRL,
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L0_RX_SIGDET_EN | L0_RX_TERM_MODE(1) | L0_RX_I_EN},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL,
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BIAS_EN | PLL_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN |
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PLL_RXCLK_EN},
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{EMAC_SGMII_PHY_LANE_CTRL1,
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L0_RX_EQUALIZE_ENABLE | L0_RESET_TSYNC_EN | L0_DRV_LVL(15)},
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};
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static const struct emac_reg_write sysclk_refclk_setting[] = {
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{EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
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{EMAC_QSERDES_COM_SYS_CLK_CTRL, SYSCLK_CM | SYSCLK_AC_COUPLE},
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};
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static const struct emac_reg_write pll_setting[] = {
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{EMAC_QSERDES_COM_PLL_IP_SETI, PLL_IPSETI(1)},
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{EMAC_QSERDES_COM_PLL_CP_SETI, PLL_CPSETI(59)},
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{EMAC_QSERDES_COM_PLL_IP_SETP, PLL_IPSETP(10)},
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{EMAC_QSERDES_COM_PLL_CP_SETP, PLL_CPSETP(9)},
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{EMAC_QSERDES_COM_PLL_CRCTRL, PLL_RCTRL(15) | PLL_CCTRL(11)},
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{EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN | PLL_DIV_ORD},
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{EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX | DEC_START1(2)},
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{EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX | DEC_START2},
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{EMAC_QSERDES_COM_DIV_FRAC_START1,
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DIV_FRAC_START_MUX | DIV_FRAC_START(85)},
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{EMAC_QSERDES_COM_DIV_FRAC_START2,
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DIV_FRAC_START_MUX | DIV_FRAC_START(42)},
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{EMAC_QSERDES_COM_DIV_FRAC_START3,
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DIV_FRAC_START3_MUX | DIV_FRAC_START3(3)},
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{EMAC_QSERDES_COM_PLLLOCK_CMP1, PLLLOCK_CMP(43)},
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{EMAC_QSERDES_COM_PLLLOCK_CMP2, PLLLOCK_CMP(104)},
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{EMAC_QSERDES_COM_PLLLOCK_CMP3, PLLLOCK_CMP(0)},
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{EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
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{EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
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};
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static const struct emac_reg_write cdr_setting[] = {
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{EMAC_QSERDES_RX_CDR_CONTROL,
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SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(2)},
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{EMAC_QSERDES_RX_CDR_CONTROL2,
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SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(4)},
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};
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static const struct emac_reg_write tx_rx_setting[] = {
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{EMAC_QSERDES_TX_BIST_MODE_LANENO, 0},
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{EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX | TX_DRV_LVL(15)},
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{EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
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{EMAC_QSERDES_TX_TX_EMP_POST1_LVL,
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TX_EMP_POST1_LVL_MUX | TX_EMP_POST1_LVL(1)},
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{EMAC_QSERDES_RX_RX_EQ_GAIN12, RX_EQ_GAIN2(15) | RX_EQ_GAIN1(15)},
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{EMAC_QSERDES_TX_LANE_MODE, LANE_MODE(8)},
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};
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int emac_sgmii_init_fsm9900(struct emac_adapter *adpt)
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{
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struct emac_sgmii *phy = &adpt->phy;
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unsigned int i;
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emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
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ARRAY_SIZE(physical_coding_sublayer_programming));
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emac_reg_write_all(phy->base, sysclk_refclk_setting,
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ARRAY_SIZE(sysclk_refclk_setting));
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emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting));
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emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting));
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emac_reg_write_all(phy->base, tx_rx_setting, ARRAY_SIZE(tx_rx_setting));
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/* Power up the Ser/Des engine */
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writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
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for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
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if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY)
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break;
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usleep_range(100, 200);
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}
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if (i == SERDES_START_WAIT_TIMES) {
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netdev_err(adpt->netdev, "error: ser/des failed to start\n");
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return -EIO;
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}
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/* Mask out all the SGMII Interrupt */
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writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
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return 0;
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}
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