/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#ifndef _IXGBE_FCOE_H
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#define _IXGBE_FCOE_H
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#include <scsi/fc/fc_fs.h>
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#include <scsi/fc/fc_fcoe.h>
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/* shift bits within STAT fo FCSTAT */
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#define IXGBE_RXDADV_FCSTAT_SHIFT 4
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/* ddp user buffer */
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#define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */
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#define IXGBE_FCPTR_ALIGN 16
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#define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
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#define IXGBE_FCBUFF_4KB 0x0
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#define IXGBE_FCBUFF_8KB 0x1
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#define IXGBE_FCBUFF_16KB 0x2
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#define IXGBE_FCBUFF_64KB 0x3
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#define IXGBE_FCBUFF_MAX 65536 /* 64KB max */
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#define IXGBE_FCBUFF_MIN 4096 /* 4KB min */
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#define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */
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#define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */
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/* Default traffic class to use for FCoE */
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#define IXGBE_FCOE_DEFTC 3
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/* fcerr */
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#define IXGBE_FCERR_BADCRC 0x00100000
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/* FCoE DDP for target mode */
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#define __IXGBE_FCOE_TARGET 1
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struct ixgbe_fcoe_ddp {
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int len;
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u32 err;
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unsigned int sgc;
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struct scatterlist *sgl;
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dma_addr_t udp;
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u64 *udl;
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struct dma_pool *pool;
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};
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/* per cpu variables */
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struct ixgbe_fcoe_ddp_pool {
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struct dma_pool *pool;
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u64 noddp;
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u64 noddp_ext_buff;
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};
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struct ixgbe_fcoe {
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struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool;
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atomic_t refcnt;
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spinlock_t lock;
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struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550];
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void *extra_ddp_buffer;
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dma_addr_t extra_ddp_buffer_dma;
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unsigned long mode;
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u8 up;
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};
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#endif /* _IXGBE_FCOE_H */
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