/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2018 Intel Corporation. */
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#ifndef I40E_TXRX_COMMON_
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#define I40E_TXRX_COMMON_
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int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring);
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void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
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u64 qword1);
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void i40e_process_skb_fields(struct i40e_ring *rx_ring,
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union i40e_rx_desc *rx_desc, struct sk_buff *skb);
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void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring);
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void i40e_update_rx_stats(struct i40e_ring *rx_ring,
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unsigned int total_rx_bytes,
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unsigned int total_rx_packets);
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void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res);
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void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val);
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#define I40E_XDP_PASS 0
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#define I40E_XDP_CONSUMED BIT(0)
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#define I40E_XDP_TX BIT(1)
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#define I40E_XDP_REDIR BIT(2)
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/*
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* build_ctob - Builds the Tx descriptor (cmd, offset and type) qword
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*/
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static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
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u32 td_tag)
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{
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return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
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((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
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((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
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((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
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((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
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}
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/**
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* i40e_update_tx_stats - Update the egress statistics for the Tx ring
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* @tx_ring: Tx ring to update
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* @total_packets: total packets sent
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* @total_bytes: total bytes sent
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**/
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static inline void i40e_update_tx_stats(struct i40e_ring *tx_ring,
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unsigned int total_packets,
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unsigned int total_bytes)
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{
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u64_stats_update_begin(&tx_ring->syncp);
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tx_ring->stats.bytes += total_bytes;
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tx_ring->stats.packets += total_packets;
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u64_stats_update_end(&tx_ring->syncp);
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tx_ring->q_vector->tx.total_bytes += total_bytes;
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tx_ring->q_vector->tx.total_packets += total_packets;
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}
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#define WB_STRIDE 4
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/**
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* i40e_arm_wb - (Possibly) arms Tx write-back
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* @tx_ring: Tx ring to update
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* @vsi: the VSI
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* @budget: the NAPI budget left
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**/
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static inline void i40e_arm_wb(struct i40e_ring *tx_ring,
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struct i40e_vsi *vsi,
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int budget)
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{
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if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
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/* check to see if there are < 4 descriptors
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* waiting to be written back, then kick the hardware to force
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* them to be written back in case we stay in NAPI.
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* In this mode on X722 we do not enable Interrupt.
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*/
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unsigned int j = i40e_get_tx_pending(tx_ring, false);
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if (budget &&
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((j / WB_STRIDE) == 0) && j > 0 &&
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!test_bit(__I40E_VSI_DOWN, vsi->state) &&
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(I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
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tx_ring->arm_wb = true;
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}
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}
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/**
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* i40e_rx_is_programming_status - check for programming status descriptor
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* @qword1: qword1 representing status_error_len in CPU ordering
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*
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* The value of in the descriptor length field indicate if this
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* is a programming status descriptor for flow director or FCoE
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* by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
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* it is a packet descriptor.
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**/
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static inline bool i40e_rx_is_programming_status(u64 qword1)
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{
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/* The Rx filter programming status and SPH bit occupy the same
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* spot in the descriptor. Since we don't support packet split we
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* can just reuse the bit as an indication that this is a
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* programming status descriptor.
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*/
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return qword1 & I40E_RXD_QW1_LENGTH_SPH_MASK;
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}
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void i40e_xsk_clean_rx_ring(struct i40e_ring *rx_ring);
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void i40e_xsk_clean_tx_ring(struct i40e_ring *tx_ring);
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bool i40e_xsk_any_rx_ring_enabled(struct i40e_vsi *vsi);
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#endif /* I40E_TXRX_COMMON_ */
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