/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2014-2015 Hisilicon Limited.
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*/
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#ifndef _HNS_DSAF_PPE_H
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#define _HNS_DSAF_PPE_H
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#include <linux/platform_device.h>
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#include "hns_dsaf_main.h"
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#include "hns_dsaf_mac.h"
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#include "hns_dsaf_rcb.h"
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#define HNS_PPE_SERVICE_NW_ENGINE_NUM DSAF_COMM_CHN
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#define HNS_PPE_DEBUG_NW_ENGINE_NUM 1
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#define HNS_PPE_COM_NUM DSAF_COMM_DEV_NUM
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#define PPE_COMMON_REG_OFFSET 0x70000
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#define PPE_REG_OFFSET 0x10000
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#define ETH_PPE_DUMP_NUM 576
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#define ETH_PPE_STATIC_NUM 12
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#define HNS_PPEV2_RSS_IND_TBL_SIZE 256
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#define HNS_PPEV2_RSS_KEY_SIZE 40 /* in bytes or 320 bits */
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#define HNS_PPEV2_RSS_KEY_NUM (HNS_PPEV2_RSS_KEY_SIZE / sizeof(u32))
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#define HNS_PPEV2_MAX_FRAME_LEN 0X980
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enum ppe_qid_mode {
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PPE_QID_MODE0 = 0, /* fixed queue id mode */
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PPE_QID_MODE1, /* switch:128VM non switch:6Port/4VM/4TC */
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PPE_QID_MODE2, /* switch:32VM/4TC non switch:6Port/16VM */
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PPE_QID_MODE3, /* switch:4TC/8RSS non switch:2Port/64VM */
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PPE_QID_MODE4, /* switch:8VM/16RSS non switch:2Port/16VM/4TC */
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PPE_QID_MODE5, /* switch:16VM/8TC non switch:6Port/16RSS */
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PPE_QID_MODE6, /* switch:32VM/4RSS non switch:6Port/2VM/8TC */
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PPE_QID_MODE7, /* switch:32RSS non switch:2Port/8VM/8TC */
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PPE_QID_MODE8, /* switch:6VM/4TC/4RSS non switch:2Port/16VM/4RSS */
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PPE_QID_MODE9, /* non switch:2Port/32VM/2RSS */
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PPE_QID_MODE10, /* non switch:2Port/32RSS */
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PPE_QID_MODE11, /* non switch:2Port/4TC/16RSS */
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};
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enum ppe_port_mode {
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PPE_MODE_GE = 0,
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PPE_MODE_XGE,
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};
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enum ppe_common_mode {
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PPE_COMMON_MODE_DEBUG = 0,
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PPE_COMMON_MODE_SERVICE,
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PPE_COMMON_MODE_MAX
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};
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struct hns_ppe_hw_stats {
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u64 rx_pkts_from_sw;
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u64 rx_pkts;
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u64 rx_drop_no_bd;
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u64 rx_alloc_buf_fail;
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u64 rx_alloc_buf_wait;
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u64 rx_drop_no_buf;
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u64 rx_err_fifo_full;
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u64 tx_bd_form_rcb;
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u64 tx_pkts_from_rcb;
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u64 tx_pkts;
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u64 tx_err_fifo_empty;
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u64 tx_err_checksum;
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};
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struct hns_ppe_cb {
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struct device *dev;
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struct hns_ppe_cb *next; /* pointer to next ppe device */
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struct ppe_common_cb *ppe_common_cb; /* belong to */
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struct hns_ppe_hw_stats hw_stats;
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u8 index; /* index in a ppe common device */
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u8 __iomem *io_base;
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int virq;
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u32 rss_indir_table[HNS_PPEV2_RSS_IND_TBL_SIZE]; /*shadow indir tab */
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u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]; /* rss hash key */
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};
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struct ppe_common_cb {
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struct device *dev;
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struct dsaf_device *dsaf_dev;
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u8 __iomem *io_base;
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enum ppe_common_mode ppe_mode;
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u8 comm_index; /*ppe_common index*/
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u32 ppe_num;
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struct hns_ppe_cb ppe_cb[];
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};
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int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb);
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int hns_ppe_init(struct dsaf_device *dsaf_dev);
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void hns_ppe_uninit(struct dsaf_device *dsaf_dev);
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void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index);
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void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb);
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int hns_ppe_get_sset_count(int stringset);
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int hns_ppe_get_regs_count(void);
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void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data);
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void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data);
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void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data);
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void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value);
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void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
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const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]);
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void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
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const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]);
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#endif /* _HNS_DSAF_PPE_H */
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