/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef FS_ENET_FEC_H
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#define FS_ENET_FEC_H
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#define FEC_MAX_MULTICAST_ADDRS 64
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/* Interrupt events/masks.
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*/
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#define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
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#define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
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#define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
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#define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
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#define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
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#define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
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#define FEC_ENET_RXF 0x02000000U /* Full frame received */
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#define FEC_ENET_RXB 0x01000000U /* A buffer was received */
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#define FEC_ENET_MII 0x00800000U /* MII interrupt */
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#define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
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#define FEC_ECNTRL_PINMUX 0x00000004
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#define FEC_ECNTRL_ETHER_EN 0x00000002
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#define FEC_ECNTRL_RESET 0x00000001
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/* RMII mode enabled only when MII_MODE bit is set too. */
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#define FEC_RCNTRL_RMII_MODE (0x00000100 | \
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FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE)
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#define FEC_RCNTRL_FCE 0x00000020
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#define FEC_RCNTRL_BC_REJ 0x00000010
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#define FEC_RCNTRL_PROM 0x00000008
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#define FEC_RCNTRL_MII_MODE 0x00000004
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#define FEC_RCNTRL_DRT 0x00000002
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#define FEC_RCNTRL_LOOP 0x00000001
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#define FEC_TCNTRL_FDEN 0x00000004
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#define FEC_TCNTRL_HBC 0x00000002
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#define FEC_TCNTRL_GTS 0x00000001
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/*
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* Delay to wait for FEC reset command to complete (in us)
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*/
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#define FEC_RESET_DELAY 50
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#endif
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