// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd
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*
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* Authors:
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* Dingqiang Lin <jon.lin@rock-chips.com>
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_HYF 0xC9
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int hyf1gq4upacae_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 64;
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region->length = 64;
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return 0;
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}
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static int hyf1gq4upacae_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 1;
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region->length = 63;
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return 0;
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}
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static const struct mtd_ooblayout_ops hyf1gq4upacae_ooblayout = {
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.ecc = hyf1gq4upacae_ooblayout_ecc,
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.free = hyf1gq4upacae_ooblayout_free,
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};
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static int hyf1gq4udacae_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 8;
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region->length = 8;
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return 0;
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}
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static int hyf1gq4udacae_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 4;
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region->length = 4;
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return 0;
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}
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static const struct mtd_ooblayout_ops hyf1gq4udacae_ooblayout = {
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.ecc = hyf1gq4udacae_ooblayout_ecc,
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.free = hyf1gq4udacae_ooblayout_free,
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};
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static int hyf2gq4uaacae_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (32 * section) + 8;
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region->length = 24;
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return 0;
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}
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static int hyf2gq4uaacae_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = 32 * section;
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region->length = 8;
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return 0;
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}
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static const struct mtd_ooblayout_ops hyf2gq4uaacae_ooblayout = {
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.ecc = hyf2gq4uaacae_ooblayout_ecc,
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.free = hyf2gq4uaacae_ooblayout_free,
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};
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static int hyf1gq4udacae_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case STATUS_ECC_HAS_BITFLIPS:
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return 1;
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default:
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return nanddev_get_ecc_requirements(nand)->strength;
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}
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return -EINVAL;
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}
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static const struct spinand_info hyf_spinand_table[] = {
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SPINAND_INFO("HYF1GQ4UPACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xA1),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf1gq4upacae_ooblayout, NULL)),
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SPINAND_INFO("HYF1GQ4UDACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF1GQ4UDACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x22),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF2GQ4UAACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(14, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF2GQ4UHCCAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x5A),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(14, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF4GQ4UAACBE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xD4),
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NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF2GQ4IAACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 20, 1, 1, 1),
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NAND_ECCREQ(14, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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SPINAND_INFO("HYF1GQ4IDACAE",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x81),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 10, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout,
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hyf1gq4udacae_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops hyf_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer hyf_spinand_manufacturer = {
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.id = SPINAND_MFR_HYF,
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.name = "hyf",
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.chips = hyf_spinand_table,
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.nchips = ARRAY_SIZE(hyf_spinand_table),
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.ops = &hyf_spinand_manuf_ops,
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};
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