/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Guochun Huang <hero.huang@rock-chips.com>
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*/
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#ifndef RK628_GVI_H
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#define RK628_GVI_H
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#include "rk628.h"
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#define GVI_BASE 0x80000
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#define HOSTREG(x) ((x) + GVI_BASE)
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#define GVI_SYS_CTRL0 HOSTREG(0x0000)
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#define GVI_SYS_CTRL1 HOSTREG(0x0004)
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#define GVI_SYS_CTRL2 HOSTREG(0x0008)
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#define GVI_SYS_CTRL3 HOSTREG(0x000c)
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#define GVI_VERSION HOSTREG(0x0010)
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#define GVI_SYS_RST HOSTREG(0x0014)
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#define GVI_LINE_FLAG HOSTREG(0x0018)
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#define GVI_STATUS HOSTREG(0x001c)
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#define GVI_PLL_LOCK_TIMEOUT HOSTREG(0x0030)
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#define GVI_HTPDN_TIMEOUT HOSTREG(0x0034)
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#define GVI_LOCKN_TIMEOUT HOSTREG(0x0038)
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#define GVI_WAIT_LOCKN HOSTREG(0x003C)
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#define GVI_WAIT_HTPDN HOSTREG(0x0040)
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#define GVI_INTR_EN HOSTREG(0x0050)
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#define GVI_INTR_CLR HOSTREG(0x0054)
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#define GVI_INTR_RAW_STATUS HOSTREG(0x0058)
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#define GVI_INTR_STATUS HOSTREG(0x005c)
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#define GVI_COLOR_BAR_CTRL HOSTREG(0x0060)
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#define GVI_COLOR_BAR_HTIMING0 HOSTREG(0x0070)
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#define GVI_COLOR_BAR_HTIMING1 HOSTREG(0x0074)
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#define GVI_COLOR_BAR_VTIMING0 HOSTREG(0x0078)
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#define GVI_COLOR_BAR_VTIMING1 HOSTREG(0x007c)
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/* SYS_CTRL0 */
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#define SYS_CTRL0_GVI_EN BIT(0)
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#define SYS_CTRL0_AUTO_GATING BIT(1)
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#define SYS_CTRL0_FRM_RST_EN BIT(2)
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#define SYS_CTRL0_FRM_RST_MODE BIT(3)
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#define SYS_CTRL0_LANE_NUM_MASK GENMASK(7, 4)
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#define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
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#define SYS_CTRL0_BYTE_MODE_MASK GENMASK(9, 8)
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#define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
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#define SYS_CTRL0_SECTION_NUM_MASK GENMASK(11, 10)
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#define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
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#define SYS_CTRL0_CDR_ENDIAN_SWAP BIT(12)
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#define SYS_CTRL0_PACK_BYTE_SWAP BIT(13)
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#define SYS_CTRL0_PACK_ENDIAN_SWAP BIT(14)
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#define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP BIT(15)
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#define SYS_CTRL0_CDR_EN BIT(16)
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#define SYS_CTRL0_ALN_EN BIT(17)
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#define SYS_CTRL0_NOR_EN BIT(18)
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#define SYS_CTRL0_ALN_NOR_MODE BIT(19)
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#define SYS_CTRL0_GVI_MASK GENMASK(19, 16)
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#define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
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#define SYS_CTRL0_SCRAMBLER_EN BIT(20)
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#define SYS_CTRL0_ENCODE8B10B_EN BIT(21)
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#define SYS_CTRL0_INIT_RD_EN BIT(22)
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#define SYS_CTRL0_INIT_RD_VALUE BIT(23)
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#define SYS_CTRL0_FORCE_HTPDN_EN BIT(24)
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#define SYS_CTRL0_FORCE_HTPDN_VALUE BIT(25)
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#define SYS_CTRL0_FORCE_PLL_EN BIT(26)
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#define SYS_CTRL0_FORCE_PLL_VALUE BIT(27)
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#define SYS_CTRL0_FORCE_LOCKN_EN BIT(28)
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#define SYS_CTRL0_FORCE_LOCKN_VALUE BIT(29)
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/* SYS_CTRL1 */
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#define SYS_CTRL1_COLOR_DEPTH_MASK GENMASK(3, 0)
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#define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
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#define SYS_CTRL1_DUAL_PIXEL_EN BIT(4)
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#define SYS_CTRL1_TIMING_ALIGN_EN BIT(8)
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#define SYS_CTRL1_LANE_ALIGN_EN BIT(9)
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#define SYS_CTRL1_DUAL_PIXEL_SWAP BIT(12)
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#define SYS_CTRL1_RB_SWAP BIT(13)
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#define SYS_CTRL1_YC_SWAP BIT(14)
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#define SYS_CTRL1_WHOLE_FRM_EN BIT(16)
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#define SYS_CTRL1_NOR_PROTECT BIT(17)
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#define SYS_CTRL1_RD_WCNT_UPDATE BIT(31)
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/* SYS_CTRL2 */
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#define SYS_CTRL2_AFIFO_READ_THOLD_MASK GENMASK(7, 0)
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#define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
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#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK GENMASK(23, 16)
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#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
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#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK GENMASK(31, 24)
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#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
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/* SYS_CTRL3 */
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#define SYS_CTRL3_LANE0_SEL_MASK GENMASK(2, 0)
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#define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
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#define SYS_CTRL3_LANE1_SEL_MASK GENMASK(6, 4)
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#define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
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#define SYS_CTRL3_LANE2_SEL_MASK GENMASK(10, 8)
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#define SYS_CTRL3_LANE2_SEL(x) UPDATE(x, 10, 8)
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#define SYS_CTRL3_LANE3_SEL_MASK GENMASK(14, 12)
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#define SYS_CTRL3_LANE3_SEL(x) UPDATE(x, 14, 12)
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#define SYS_CTRL3_LANE4_SEL_MASK GENMASK(18, 16)
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#define SYS_CTRL3_LANE4_SEL(x) UPDATE(x, 18, 16)
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#define SYS_CTRL3_LANE5_SEL_MASK GENMASK(22, 20)
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#define SYS_CTRL3_LANE5_SEL(x) UPDATE(x, 22, 20)
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#define SYS_CTRL3_LANE6_SEL_MASK GENMASK(26, 24)
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#define SYS_CTRL3_LANE6_SEL(x) UPDATE(x, 26, 24)
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#define SYS_CTRL3_LANE7_SEL_MASK GENMASK(30, 28)
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#define SYS_CTRL3_LANE7_SEL(x) UPDATE(x, 30, 28)
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/* VERSIION */
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#define VERSION_VERSION(x) UPDATE(x, 31, 0)
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/* SYS_RESET*/
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#define SYS_RST_SOFT_RST BIT(0)
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/* LINE_FLAG */
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#define LINE_FLAG_LANE_FLAG0_MASK GENMASK(15, 0)
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#define LINE_FLAG_LANE_FLAG0(x) UPDATE(x, 15, 0)
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#define LINE_FLAG_LANE_FLAG1_MASK GENMASK(31, 16)
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#define LINE_FLAG_LANE_FLAG1(x) UPDATE(x, 31, 16)
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/* STATUS */
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#define STATUS_HTDPN BIT(4)
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#define STATUS_LOCKN BIT(5)
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#define STATUS_PLL_LOCKN BIT(6)
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#define STATUS_AFIFO0_WCNT_MASK GENMASK(23, 16)
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#define STATUS_AFIFO0_WCNT(x) UPDATE(x, 23, 16)
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#define STATUS_AFIFO1_WCNT_MASK GENMASK(31, 24)
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#define STATUS_AFIFO1_WCNT(x) UPDATE(x, 31, 24)
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/* PLL_LTIMEOUT */
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#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK GENMASK(31, 0)
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#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x) UPDATE(x, 31, 0)
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/* HTPDNEOUT */
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#define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK GENMASK(31, 0)
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#define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x) UPDATE(x, 31, 0)
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/* LOCKNEOUT */
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#define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK GENMASK(31, 0)
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#define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x) UPDATE(x, 31, 0)
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/* WAIT_LOCKN */
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#define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK GENMASK(30, 0)
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#define WAIT_LOCKN_WAIT_LOCKN_TIME(x) UPDATE(x, 30, 0)
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#define WAIT_LOCKN_WAIT_LOCKN_TIME_EN BIT(31)
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/* WAIT_HTPDN */
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#define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK GENMASK(30, 0)
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#define WAIT_HTPDN_WAIT_HTPDN_TIME(x) UPDATE(x, 30, 0)
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#define WAIT_HTPDN_WAIT_HTPDN_EN BIT(31)
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/* INTR_EN */
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#define INTR_EN_INTR_FRM_ST_EN BIT(0)
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#define INTR_EN_INTR_PLL_LOCK_EN BIT(1)
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#define INTR_EN_INTR_HTPDN_EN BIT(2)
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#define INTR_EN_INTR_LOCKN_EN BIT(3)
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#define INTR_EN_INTR_PLL_TIMEOUT_EN BIT(4)
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#define INTR_EN_INTR_HTPDN_TIMEOUT_EN BIT(5)
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#define INTR_EN_INTR_LOCKN_TIMEOUT_EN BIT(6)
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#define INTR_EN_INTR_LINE_FLAG0_EN BIT(8)
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#define INTR_EN_INTR_LINE_FLAG1_EN BIT(9)
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#define INTR_EN_INTR_AFIFO_OVERFLOW_EN BIT(10)
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#define INTR_EN_INTR_AFIFO_UNDERFLOW_EN BIT(11)
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#define INTR_EN_INTR_PLL_ERR_EN BIT(12)
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#define INTR_EN_INTR_HTPDN_ERR_EN BIT(13)
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#define INTR_EN_INTR_LOCKN_ERR_EN BIT(14)
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/* INTR_CLR*/
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#define INTR_CLR_INTR_FRM_ST_CLR BIT(0)
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#define INTR_CLR_INTR_PLL_LOCK_CLR BIT(1)
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#define INTR_CLR_INTR_HTPDN_CLR BIT(2)
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#define INTR_CLR_INTR_LOCKN_CLR BIT(3)
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#define INTR_CLR_INTR_PLL_TIMEOUT_CLR BIT(4)
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#define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR BIT(5)
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#define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR BIT(6)
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#define INTR_CLR_INTR_LINE_FLAG0_CLR BIT(8)
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#define INTR_CLR_INTR_LINE_FLAG1_CLR BIT(9)
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#define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR BIT(10)
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#define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR BIT(11)
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#define INTR_CLR_INTR_PLL_ERR_CLR BIT(12)
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#define INTR_CLR_INTR_HTPDN_ERR_CLR BIT(13)
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#define INTR_CLR_INTR_LOCKN_ERR_CLR BIT(14)
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/* INTR_RAW_STATUS */
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#define INTR_RAW_STATUS_RAW_INTR_FRM_ST BIT(0)
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#define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK BIT(1)
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#define INTR_RAW_STATUS_RAW_INTR_HTPDN BIT(2)
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#define INTR_RAW_STATUS_RAW_INTR_LOCKN BIT(3)
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#define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT BIT(4)
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#define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT BIT(5)
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#define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT BIT(6)
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#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0 BIT(8)
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#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1 BIT(9)
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#define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW BIT(10)
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#define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW BIT(11)
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#define INTR_RAW_STATUS_RAW_INTR_PLL_ERR BIT(12)
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#define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR BIT(13)
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#define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR BIT(14)
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/* INTR_STATUS */
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#define INTR_STATUS_INTR_FRM_ST BIT(0)
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#define INTR_STATUS_INTR_PLL_LOCK BIT(1)
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#define INTR_STATUS_INTR_HTPDN BIT(2)
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#define INTR_STATUS_INTR_LOCKN BIT(3)
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#define INTR_STATUS_INTR_PLL_TIMEOUT BIT(4)
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#define INTR_STATUS_INTR_HTPDN_TIMEOUT BIT(5)
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#define INTR_STATUS_INTR_LOCKN_TIMEOUT BIT(6)
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#define INTR_STATUS_INTR_LINE_FLAG0 BIT(8)
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#define INTR_STATUS_INTR_LINE_FLAG1 BIT(9)
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#define INTR_STATUS_INTR_AFIFO_OVERFLOW BIT(10)
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#define INTR_STATUS_INTR_AFIFO_UNDERFLOW BIT(11)
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#define INTR_STATUS_INTR_PLL_ERR BIT(12)
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#define INTR_STATUS_INTR_HTPDN_ERR BIT(13)
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#define INTR_STATUS_INTR_LOCKN_ERR BIT(14)
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/* COLOR_BAR_CTRL */
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#define COLOR_BAR_EN BIT(0)
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#define COLOR_DEPTH_RGB_YUV444_18BIT 0
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#define COLOR_DEPTH_RGB_YUV444_24BIT 1
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#define COLOR_DEPTH_RGB_YUV444_30BIT 2
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#define COLOR_DEPTH_YUV422_16BIT 8
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#define COLOR_DEPTH_YUV422_20BIT 9
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int rk628_gvi_parse(struct rk628 *rk628, struct device_node *gvi_np);
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void rk628_gvi_enable(struct rk628 *rk628);
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void rk628_gvi_disable(struct rk628 *rk628);
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#endif
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