/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC_PLL_REGS_H_
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#define ASIC_REG_TPC_PLL_REGS_H_
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/*
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*****************************************
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* TPC_PLL (Prototype: PLL)
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*****************************************
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*/
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#define mmTPC_PLL_NR 0xE01100
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#define mmTPC_PLL_NF 0xE01104
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#define mmTPC_PLL_OD 0xE01108
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#define mmTPC_PLL_NB 0xE0110C
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#define mmTPC_PLL_CFG 0xE01110
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#define mmTPC_PLL_LOSE_MASK 0xE01120
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#define mmTPC_PLL_LOCK_INTR 0xE01128
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#define mmTPC_PLL_LOCK_BYPASS 0xE0112C
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#define mmTPC_PLL_DATA_CHNG 0xE01130
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#define mmTPC_PLL_RST 0xE01134
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#define mmTPC_PLL_SLIP_WD_CNTR 0xE01150
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#define mmTPC_PLL_DIV_FACTOR_0 0xE01200
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#define mmTPC_PLL_DIV_FACTOR_1 0xE01204
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#define mmTPC_PLL_DIV_FACTOR_2 0xE01208
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#define mmTPC_PLL_DIV_FACTOR_3 0xE0120C
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#define mmTPC_PLL_DIV_FACTOR_CMD_0 0xE01220
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#define mmTPC_PLL_DIV_FACTOR_CMD_1 0xE01224
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#define mmTPC_PLL_DIV_FACTOR_CMD_2 0xE01228
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#define mmTPC_PLL_DIV_FACTOR_CMD_3 0xE0122C
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#define mmTPC_PLL_DIV_SEL_0 0xE01280
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#define mmTPC_PLL_DIV_SEL_1 0xE01284
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#define mmTPC_PLL_DIV_SEL_2 0xE01288
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#define mmTPC_PLL_DIV_SEL_3 0xE0128C
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#define mmTPC_PLL_DIV_EN_0 0xE012A0
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#define mmTPC_PLL_DIV_EN_1 0xE012A4
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#define mmTPC_PLL_DIV_EN_2 0xE012A8
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#define mmTPC_PLL_DIV_EN_3 0xE012AC
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#define mmTPC_PLL_DIV_FACTOR_BUSY_0 0xE012C0
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#define mmTPC_PLL_DIV_FACTOR_BUSY_1 0xE012C4
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#define mmTPC_PLL_DIV_FACTOR_BUSY_2 0xE012C8
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#define mmTPC_PLL_DIV_FACTOR_BUSY_3 0xE012CC
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#define mmTPC_PLL_CLK_GATER 0xE01300
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#define mmTPC_PLL_CLK_RLX_0 0xE01310
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#define mmTPC_PLL_CLK_RLX_1 0xE01314
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#define mmTPC_PLL_CLK_RLX_2 0xE01318
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#define mmTPC_PLL_CLK_RLX_3 0xE0131C
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#define mmTPC_PLL_REF_CNTR_PERIOD 0xE01400
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#define mmTPC_PLL_REF_LOW_THRESHOLD 0xE01410
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#define mmTPC_PLL_REF_HIGH_THRESHOLD 0xE01420
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#define mmTPC_PLL_PLL_NOT_STABLE 0xE01430
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#define mmTPC_PLL_FREQ_CALC_EN 0xE01440
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#endif /* ASIC_REG_TPC_PLL_REGS_H_ */
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