/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC7_CFG_REGS_H_
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#define ASIC_REG_TPC7_CFG_REGS_H_
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/*
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*****************************************
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* TPC7_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400
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#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404
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#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408
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#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6418
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC641C
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC6420
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6424
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6428
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC642C
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6430
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6434
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC6438
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xFC643C
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6440
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6444
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#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6448
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#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC644C
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#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC6450
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#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6454
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#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6458
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC645C
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC6460
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6464
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6468
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC646C
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6470
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6474
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC6478
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xFC647C
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6480
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6484
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6488
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC648C
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC6490
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#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6494
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#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6498
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#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC649C
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#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC64A0
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#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC64A4
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC64A8
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC64AC
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xFC64B0
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC64B4
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC64B8
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xFC64BC
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC64C0
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC64C4
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xFC64C8
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC64CC
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC64D0
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xFC64D4
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64D8
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64DC
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#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xFC64E0
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#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64E4
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#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64E8
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#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64EC
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#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64F0
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64F4
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64F8
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xFC64FC
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC6500
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC6504
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6508
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC650C
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC6510
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6514
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC6518
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC651C
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6520
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC6524
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC6528
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#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xFC652C
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#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC6530
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#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC6534
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#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC6538
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#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC653C
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC6540
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC6544
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6548
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC654C
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC6550
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6554
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6558
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC655C
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6560
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6564
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC6568
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xFC656C
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6570
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6574
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#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6578
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#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC657C
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#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC6580
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#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6584
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#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6588
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC658C
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC6590
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6594
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6598
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC659C
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xFC65A0
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC65A4
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC65A8
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xFC65AC
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC65B0
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC65B4
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xFC65B8
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC65BC
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC65C0
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#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xFC65C4
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#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC65C8
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#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC65CC
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#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC65D0
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#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC65D4
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC65D8
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC65DC
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xFC65E0
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC65E4
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC65E8
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xFC65EC
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC65F0
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC65F4
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xFC65F8
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC65FC
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC6600
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6604
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6608
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC660C
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#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6610
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#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6614
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#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC6618
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#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC661C
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#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6620
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6624
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC6628
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xFC662C
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC6630
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC6634
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6638
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC663C
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC6640
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6644
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC6648
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC664C
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6650
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC6654
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC6658
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#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xFC665C
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#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6660
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#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC6664
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#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6668
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#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC666C
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#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6670
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#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC6674
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#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC6678
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#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC667C
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#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC6680
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#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC6684
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#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC6688
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#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC668C
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#define mmTPC7_CFG_KERNEL_SRF_0 0xFC6690
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#define mmTPC7_CFG_KERNEL_SRF_1 0xFC6694
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#define mmTPC7_CFG_KERNEL_SRF_2 0xFC6698
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#define mmTPC7_CFG_KERNEL_SRF_3 0xFC669C
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#define mmTPC7_CFG_KERNEL_SRF_4 0xFC66A0
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#define mmTPC7_CFG_KERNEL_SRF_5 0xFC66A4
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#define mmTPC7_CFG_KERNEL_SRF_6 0xFC66A8
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#define mmTPC7_CFG_KERNEL_SRF_7 0xFC66AC
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#define mmTPC7_CFG_KERNEL_SRF_8 0xFC66B0
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#define mmTPC7_CFG_KERNEL_SRF_9 0xFC66B4
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#define mmTPC7_CFG_KERNEL_SRF_10 0xFC66B8
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#define mmTPC7_CFG_KERNEL_SRF_11 0xFC66BC
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#define mmTPC7_CFG_KERNEL_SRF_12 0xFC66C0
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#define mmTPC7_CFG_KERNEL_SRF_13 0xFC66C4
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#define mmTPC7_CFG_KERNEL_SRF_14 0xFC66C8
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#define mmTPC7_CFG_KERNEL_SRF_15 0xFC66CC
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#define mmTPC7_CFG_KERNEL_SRF_16 0xFC66D0
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#define mmTPC7_CFG_KERNEL_SRF_17 0xFC66D4
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#define mmTPC7_CFG_KERNEL_SRF_18 0xFC66D8
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#define mmTPC7_CFG_KERNEL_SRF_19 0xFC66DC
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#define mmTPC7_CFG_KERNEL_SRF_20 0xFC66E0
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#define mmTPC7_CFG_KERNEL_SRF_21 0xFC66E4
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#define mmTPC7_CFG_KERNEL_SRF_22 0xFC66E8
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#define mmTPC7_CFG_KERNEL_SRF_23 0xFC66EC
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#define mmTPC7_CFG_KERNEL_SRF_24 0xFC66F0
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#define mmTPC7_CFG_KERNEL_SRF_25 0xFC66F4
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#define mmTPC7_CFG_KERNEL_SRF_26 0xFC66F8
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#define mmTPC7_CFG_KERNEL_SRF_27 0xFC66FC
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#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6700
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#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6704
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#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6708
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#define mmTPC7_CFG_KERNEL_SRF_31 0xFC670C
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#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC6710
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#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6714
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#define mmTPC7_CFG_RESERVED_DESC_END 0xFC6738
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#define mmTPC7_CFG_ROUND_CSR 0xFC67FC
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#define mmTPC7_CFG_TBUF_BASE_ADDR_LOW 0xFC6800
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#define mmTPC7_CFG_TBUF_BASE_ADDR_HIGH 0xFC6804
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#define mmTPC7_CFG_SEMAPHORE 0xFC6808
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#define mmTPC7_CFG_VFLAGS 0xFC680C
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#define mmTPC7_CFG_SFLAGS 0xFC6810
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#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6818
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#define mmTPC7_CFG_STATUS 0xFC681C
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#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6820
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#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6824
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#define mmTPC7_CFG_SM_BASE_ADDRESS_LOW 0xFC6828
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#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC682C
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#define mmTPC7_CFG_TPC_CMD 0xFC6830
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#define mmTPC7_CFG_TPC_EXECUTE 0xFC6838
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#define mmTPC7_CFG_TPC_STALL 0xFC683C
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#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6840
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#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6844
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#define mmTPC7_CFG_MSS_CONFIG 0xFC6854
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#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6858
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#define mmTPC7_CFG_TPC_INTR_MASK 0xFC685C
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#define mmTPC7_CFG_TSB_CONFIG 0xFC6860
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#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00
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#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04
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#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08
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#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xFC6A18
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A1C
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A20
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xFC6A24
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A28
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A2C
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xFC6A30
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A34
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A38
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xFC6A3C
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A40
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A44
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#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xFC6A48
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#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A4C
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#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A50
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#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A54
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#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A58
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A5C
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A60
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xFC6A64
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A68
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A6C
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xFC6A70
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A74
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A78
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xFC6A7C
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A80
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A84
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xFC6A88
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A8C
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A90
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#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xFC6A94
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#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A98
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#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A9C
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#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6AA0
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#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6AA4
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6AA8
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6AAC
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xFC6AB0
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6AB4
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6AB8
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xFC6ABC
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6AC0
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6AC4
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xFC6AC8
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6ACC
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6AD0
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xFC6AD4
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AD8
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6ADC
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#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xFC6AE0
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#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AE4
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#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AE8
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#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AEC
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#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AF0
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AF4
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6AF8
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xFC6AFC
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6B00
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6B04
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xFC6B08
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6B0C
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6B10
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xFC6B14
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6B18
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6B1C
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xFC6B20
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6B24
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6B28
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#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xFC6B2C
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#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6B30
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#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6B34
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#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6B38
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#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6B3C
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6B40
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6B44
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xFC6B48
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6B4C
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6B50
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xFC6B54
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B58
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B5C
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xFC6B60
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B64
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B68
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xFC6B6C
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B70
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B74
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#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xFC6B78
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#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B7C
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#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B80
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#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B84
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#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B88
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B8C
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B90
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xFC6B94
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B98
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B9C
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xFC6BA0
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6BA4
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6BA8
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xFC6BAC
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6BB0
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6BB4
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xFC6BB8
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6BBC
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6BC0
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#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xFC6BC4
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#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6BC8
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#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6BCC
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#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6BD0
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#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6BD4
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6BD8
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6BDC
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xFC6BE0
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6BE4
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6BE8
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xFC6BEC
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6BF0
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6BF4
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xFC6BF8
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6BFC
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6C00
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xFC6C04
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6C08
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6C0C
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#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xFC6C10
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#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6C14
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#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6C18
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#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6C1C
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#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6C20
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6C24
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6C28
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xFC6C2C
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6C30
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6C34
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xFC6C38
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6C3C
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6C40
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xFC6C44
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6C48
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6C4C
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xFC6C50
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6C54
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6C58
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#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xFC6C5C
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#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6C60
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#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6C64
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#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6C68
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#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6C6C
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#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6C70
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#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6C74
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#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6C78
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#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6C7C
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#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6C80
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#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6C84
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#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6C88
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#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6C8C
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#define mmTPC7_CFG_QM_SRF_0 0xFC6C90
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#define mmTPC7_CFG_QM_SRF_1 0xFC6C94
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#define mmTPC7_CFG_QM_SRF_2 0xFC6C98
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#define mmTPC7_CFG_QM_SRF_3 0xFC6C9C
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#define mmTPC7_CFG_QM_SRF_4 0xFC6CA0
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#define mmTPC7_CFG_QM_SRF_5 0xFC6CA4
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#define mmTPC7_CFG_QM_SRF_6 0xFC6CA8
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#define mmTPC7_CFG_QM_SRF_7 0xFC6CAC
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#define mmTPC7_CFG_QM_SRF_8 0xFC6CB0
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#define mmTPC7_CFG_QM_SRF_9 0xFC6CB4
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#define mmTPC7_CFG_QM_SRF_10 0xFC6CB8
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#define mmTPC7_CFG_QM_SRF_11 0xFC6CBC
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#define mmTPC7_CFG_QM_SRF_12 0xFC6CC0
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#define mmTPC7_CFG_QM_SRF_13 0xFC6CC4
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#define mmTPC7_CFG_QM_SRF_14 0xFC6CC8
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#define mmTPC7_CFG_QM_SRF_15 0xFC6CCC
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#define mmTPC7_CFG_QM_SRF_16 0xFC6CD0
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#define mmTPC7_CFG_QM_SRF_17 0xFC6CD4
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#define mmTPC7_CFG_QM_SRF_18 0xFC6CD8
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#define mmTPC7_CFG_QM_SRF_19 0xFC6CDC
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#define mmTPC7_CFG_QM_SRF_20 0xFC6CE0
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#define mmTPC7_CFG_QM_SRF_21 0xFC6CE4
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#define mmTPC7_CFG_QM_SRF_22 0xFC6CE8
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#define mmTPC7_CFG_QM_SRF_23 0xFC6CEC
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#define mmTPC7_CFG_QM_SRF_24 0xFC6CF0
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#define mmTPC7_CFG_QM_SRF_25 0xFC6CF4
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#define mmTPC7_CFG_QM_SRF_26 0xFC6CF8
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#define mmTPC7_CFG_QM_SRF_27 0xFC6CFC
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#define mmTPC7_CFG_QM_SRF_28 0xFC6D00
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#define mmTPC7_CFG_QM_SRF_29 0xFC6D04
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#define mmTPC7_CFG_QM_SRF_30 0xFC6D08
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#define mmTPC7_CFG_QM_SRF_31 0xFC6D0C
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#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6D10
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#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D14
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#define mmTPC7_CFG_ARUSER 0xFC6D18
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#define mmTPC7_CFG_AWUSER 0xFC6D1C
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#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC6E00
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#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC6E04
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#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC6E08
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#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC6E0C
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#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC6E10
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#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC6E14
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#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC6E18
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#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC6E1C
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#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC6E20
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#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC6E24
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#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC6E28
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#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC6E2C
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#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */
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