/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC6_QM_REGS_H_
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#define ASIC_REG_TPC6_QM_REGS_H_
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/*
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*****************************************
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* TPC6_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC6_QM_GLBL_CFG0 0xF88000
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#define mmTPC6_QM_GLBL_CFG1 0xF88004
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#define mmTPC6_QM_GLBL_PROT 0xF88008
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#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C
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#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88010
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#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88014
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#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88018
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#define mmTPC6_QM_GLBL_SECURE_PROPS 0xF8801C
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#define mmTPC6_QM_GLBL_NON_SECURE_PROPS 0xF88020
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#define mmTPC6_QM_GLBL_STS0 0xF88024
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#define mmTPC6_QM_GLBL_STS1 0xF88028
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#define mmTPC6_QM_PQ_BASE_LO 0xF88060
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#define mmTPC6_QM_PQ_BASE_HI 0xF88064
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#define mmTPC6_QM_PQ_SIZE 0xF88068
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#define mmTPC6_QM_PQ_PI 0xF8806C
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#define mmTPC6_QM_PQ_CI 0xF88070
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#define mmTPC6_QM_PQ_CFG0 0xF88074
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#define mmTPC6_QM_PQ_CFG1 0xF88078
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#define mmTPC6_QM_PQ_ARUSER 0xF8807C
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#define mmTPC6_QM_PQ_PUSH0 0xF88080
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#define mmTPC6_QM_PQ_PUSH1 0xF88084
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#define mmTPC6_QM_PQ_PUSH2 0xF88088
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#define mmTPC6_QM_PQ_PUSH3 0xF8808C
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#define mmTPC6_QM_PQ_STS0 0xF88090
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#define mmTPC6_QM_PQ_STS1 0xF88094
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#define mmTPC6_QM_PQ_RD_RATE_LIM_EN 0xF880A0
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#define mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF880A4
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#define mmTPC6_QM_PQ_RD_RATE_LIM_SAT 0xF880A8
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#define mmTPC6_QM_PQ_RD_RATE_LIM_TOUT 0xF880AC
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#define mmTPC6_QM_CQ_CFG0 0xF880B0
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#define mmTPC6_QM_CQ_CFG1 0xF880B4
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#define mmTPC6_QM_CQ_ARUSER 0xF880B8
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#define mmTPC6_QM_CQ_PTR_LO 0xF880C0
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#define mmTPC6_QM_CQ_PTR_HI 0xF880C4
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#define mmTPC6_QM_CQ_TSIZE 0xF880C8
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#define mmTPC6_QM_CQ_CTL 0xF880CC
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#define mmTPC6_QM_CQ_PTR_LO_STS 0xF880D4
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#define mmTPC6_QM_CQ_PTR_HI_STS 0xF880D8
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#define mmTPC6_QM_CQ_TSIZE_STS 0xF880DC
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#define mmTPC6_QM_CQ_CTL_STS 0xF880E0
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#define mmTPC6_QM_CQ_STS0 0xF880E4
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#define mmTPC6_QM_CQ_STS1 0xF880E8
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#define mmTPC6_QM_CQ_RD_RATE_LIM_EN 0xF880F0
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#define mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF880F4
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#define mmTPC6_QM_CQ_RD_RATE_LIM_SAT 0xF880F8
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#define mmTPC6_QM_CQ_RD_RATE_LIM_TOUT 0xF880FC
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#define mmTPC6_QM_CQ_IFIFO_CNT 0xF88108
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#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO 0xF88120
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#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI 0xF88124
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#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO 0xF88128
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#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI 0xF8812C
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#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO 0xF88130
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#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI 0xF88134
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#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO 0xF88138
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#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI 0xF8813C
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#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET 0xF88140
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#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF88144
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#define mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF88148
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#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF8814C
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#define mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF88150
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#define mmTPC6_QM_CP_LDMA_COMMIT_OFFSET 0xF88154
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#define mmTPC6_QM_CP_FENCE0_RDATA 0xF88158
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#define mmTPC6_QM_CP_FENCE1_RDATA 0xF8815C
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#define mmTPC6_QM_CP_FENCE2_RDATA 0xF88160
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#define mmTPC6_QM_CP_FENCE3_RDATA 0xF88164
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#define mmTPC6_QM_CP_FENCE0_CNT 0xF88168
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#define mmTPC6_QM_CP_FENCE1_CNT 0xF8816C
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#define mmTPC6_QM_CP_FENCE2_CNT 0xF88170
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#define mmTPC6_QM_CP_FENCE3_CNT 0xF88174
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#define mmTPC6_QM_CP_STS 0xF88178
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#define mmTPC6_QM_CP_CURRENT_INST_LO 0xF8817C
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#define mmTPC6_QM_CP_CURRENT_INST_HI 0xF88180
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#define mmTPC6_QM_CP_BARRIER_CFG 0xF88184
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#define mmTPC6_QM_CP_DBG_0 0xF88188
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#define mmTPC6_QM_PQ_BUF_ADDR 0xF88300
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#define mmTPC6_QM_PQ_BUF_RDATA 0xF88304
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#define mmTPC6_QM_CQ_BUF_ADDR 0xF88308
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#define mmTPC6_QM_CQ_BUF_RDATA 0xF8830C
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#endif /* ASIC_REG_TPC6_QM_REGS_H_ */
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