/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC6_CFG_REGS_H_
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#define ASIC_REG_TPC6_CFG_REGS_H_
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/*
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*****************************************
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* TPC6_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400
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#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404
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#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408
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#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF86418
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF86420
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF86424
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86428
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF86430
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86434
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF86438
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86440
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86444
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#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF86448
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#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C
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#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF86450
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#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86454
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#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86458
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF86460
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF86464
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86468
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF86470
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86474
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF86478
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86480
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86484
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF86488
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF86490
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#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF86494
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#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86498
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#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C
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#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0
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#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC
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#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0
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#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4
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#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8
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#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC
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#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528
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#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C
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#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530
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#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534
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#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538
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#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574
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#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578
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#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C
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#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580
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#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584
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#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0
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#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4
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#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8
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#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC
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#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0
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#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C
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#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610
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#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614
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#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618
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#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C
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#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658
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#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C
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#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660
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#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664
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#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668
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#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C
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#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670
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#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674
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#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678
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#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C
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#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680
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#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684
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#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688
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#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C
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#define mmTPC6_CFG_KERNEL_SRF_0 0xF86690
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#define mmTPC6_CFG_KERNEL_SRF_1 0xF86694
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#define mmTPC6_CFG_KERNEL_SRF_2 0xF86698
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#define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C
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#define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0
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#define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4
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#define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8
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#define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC
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#define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0
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#define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4
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#define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8
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#define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC
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#define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0
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#define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4
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#define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8
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#define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC
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#define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0
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#define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4
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#define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8
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#define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC
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#define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0
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#define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4
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#define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8
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#define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC
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#define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0
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#define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4
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#define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8
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#define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC
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#define mmTPC6_CFG_KERNEL_SRF_28 0xF86700
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#define mmTPC6_CFG_KERNEL_SRF_29 0xF86704
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#define mmTPC6_CFG_KERNEL_SRF_30 0xF86708
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#define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C
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#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710
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#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714
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#define mmTPC6_CFG_RESERVED_DESC_END 0xF86738
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#define mmTPC6_CFG_ROUND_CSR 0xF867FC
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#define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800
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#define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804
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#define mmTPC6_CFG_SEMAPHORE 0xF86808
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#define mmTPC6_CFG_VFLAGS 0xF8680C
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#define mmTPC6_CFG_SFLAGS 0xF86810
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#define mmTPC6_CFG_LFSR_POLYNOM 0xF86818
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#define mmTPC6_CFG_STATUS 0xF8681C
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#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820
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#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824
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#define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828
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#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C
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#define mmTPC6_CFG_TPC_CMD 0xF86830
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#define mmTPC6_CFG_TPC_EXECUTE 0xF86838
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#define mmTPC6_CFG_TPC_STALL 0xF8683C
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#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840
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#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844
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#define mmTPC6_CFG_MSS_CONFIG 0xF86854
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#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858
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#define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C
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#define mmTPC6_CFG_TSB_CONFIG 0xF86860
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#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00
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#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04
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#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08
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#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44
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#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48
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#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C
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#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50
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#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54
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#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90
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#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94
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#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98
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#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C
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#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0
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#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC
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#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0
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#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4
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#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8
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#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC
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#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28
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#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C
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#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30
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#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34
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#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38
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#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74
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#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78
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#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C
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#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80
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#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84
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#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0
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#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4
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#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8
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#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC
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#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0
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#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C
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#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10
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#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14
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#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18
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#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C
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#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58
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#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C
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#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60
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#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64
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#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68
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#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C
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#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70
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#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74
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#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78
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#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C
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#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80
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#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84
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#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88
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#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C
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#define mmTPC6_CFG_QM_SRF_0 0xF86C90
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#define mmTPC6_CFG_QM_SRF_1 0xF86C94
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#define mmTPC6_CFG_QM_SRF_2 0xF86C98
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#define mmTPC6_CFG_QM_SRF_3 0xF86C9C
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#define mmTPC6_CFG_QM_SRF_4 0xF86CA0
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#define mmTPC6_CFG_QM_SRF_5 0xF86CA4
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#define mmTPC6_CFG_QM_SRF_6 0xF86CA8
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#define mmTPC6_CFG_QM_SRF_7 0xF86CAC
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#define mmTPC6_CFG_QM_SRF_8 0xF86CB0
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#define mmTPC6_CFG_QM_SRF_9 0xF86CB4
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#define mmTPC6_CFG_QM_SRF_10 0xF86CB8
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#define mmTPC6_CFG_QM_SRF_11 0xF86CBC
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#define mmTPC6_CFG_QM_SRF_12 0xF86CC0
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#define mmTPC6_CFG_QM_SRF_13 0xF86CC4
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#define mmTPC6_CFG_QM_SRF_14 0xF86CC8
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#define mmTPC6_CFG_QM_SRF_15 0xF86CCC
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#define mmTPC6_CFG_QM_SRF_16 0xF86CD0
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#define mmTPC6_CFG_QM_SRF_17 0xF86CD4
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#define mmTPC6_CFG_QM_SRF_18 0xF86CD8
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#define mmTPC6_CFG_QM_SRF_19 0xF86CDC
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#define mmTPC6_CFG_QM_SRF_20 0xF86CE0
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#define mmTPC6_CFG_QM_SRF_21 0xF86CE4
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#define mmTPC6_CFG_QM_SRF_22 0xF86CE8
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#define mmTPC6_CFG_QM_SRF_23 0xF86CEC
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#define mmTPC6_CFG_QM_SRF_24 0xF86CF0
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#define mmTPC6_CFG_QM_SRF_25 0xF86CF4
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#define mmTPC6_CFG_QM_SRF_26 0xF86CF8
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#define mmTPC6_CFG_QM_SRF_27 0xF86CFC
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#define mmTPC6_CFG_QM_SRF_28 0xF86D00
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#define mmTPC6_CFG_QM_SRF_29 0xF86D04
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#define mmTPC6_CFG_QM_SRF_30 0xF86D08
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#define mmTPC6_CFG_QM_SRF_31 0xF86D0C
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#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10
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#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14
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#define mmTPC6_CFG_ARUSER 0xF86D18
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#define mmTPC6_CFG_AWUSER 0xF86D1C
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#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00
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#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04
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#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08
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#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C
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#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10
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#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14
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#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18
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#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C
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#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20
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#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24
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#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28
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#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C
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#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */
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