/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_
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#define ASIC_REG_TPC5_CMDQ_REGS_H_
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/*
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*****************************************
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* TPC5_CMDQ (Prototype: CMDQ)
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*****************************************
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*/
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#define mmTPC5_CMDQ_GLBL_CFG0 0xF49000
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#define mmTPC5_CMDQ_GLBL_CFG1 0xF49004
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#define mmTPC5_CMDQ_GLBL_PROT 0xF49008
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#define mmTPC5_CMDQ_GLBL_ERR_CFG 0xF4900C
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#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO 0xF49010
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#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI 0xF49014
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#define mmTPC5_CMDQ_GLBL_ERR_WDATA 0xF49018
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#define mmTPC5_CMDQ_GLBL_SECURE_PROPS 0xF4901C
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#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS 0xF49020
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#define mmTPC5_CMDQ_GLBL_STS0 0xF49024
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#define mmTPC5_CMDQ_GLBL_STS1 0xF49028
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#define mmTPC5_CMDQ_CQ_CFG0 0xF490B0
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#define mmTPC5_CMDQ_CQ_CFG1 0xF490B4
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#define mmTPC5_CMDQ_CQ_ARUSER 0xF490B8
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#define mmTPC5_CMDQ_CQ_PTR_LO 0xF490C0
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#define mmTPC5_CMDQ_CQ_PTR_HI 0xF490C4
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#define mmTPC5_CMDQ_CQ_TSIZE 0xF490C8
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#define mmTPC5_CMDQ_CQ_CTL 0xF490CC
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#define mmTPC5_CMDQ_CQ_PTR_LO_STS 0xF490D4
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#define mmTPC5_CMDQ_CQ_PTR_HI_STS 0xF490D8
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#define mmTPC5_CMDQ_CQ_TSIZE_STS 0xF490DC
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#define mmTPC5_CMDQ_CQ_CTL_STS 0xF490E0
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#define mmTPC5_CMDQ_CQ_STS0 0xF490E4
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#define mmTPC5_CMDQ_CQ_STS1 0xF490E8
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#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN 0xF490F0
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#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF490F4
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#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT 0xF490F8
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#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF490FC
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#define mmTPC5_CMDQ_CQ_IFIFO_CNT 0xF49108
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#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF49120
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#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF49124
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#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF49128
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#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF4912C
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#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF49130
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#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF49134
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#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF49138
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#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF4913C
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#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF49140
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#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF49144
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#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF49148
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#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF4914C
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#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF49150
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#define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF49154
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#define mmTPC5_CMDQ_CP_FENCE0_RDATA 0xF49158
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#define mmTPC5_CMDQ_CP_FENCE1_RDATA 0xF4915C
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#define mmTPC5_CMDQ_CP_FENCE2_RDATA 0xF49160
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#define mmTPC5_CMDQ_CP_FENCE3_RDATA 0xF49164
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#define mmTPC5_CMDQ_CP_FENCE0_CNT 0xF49168
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#define mmTPC5_CMDQ_CP_FENCE1_CNT 0xF4916C
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#define mmTPC5_CMDQ_CP_FENCE2_CNT 0xF49170
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#define mmTPC5_CMDQ_CP_FENCE3_CNT 0xF49174
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#define mmTPC5_CMDQ_CP_STS 0xF49178
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#define mmTPC5_CMDQ_CP_CURRENT_INST_LO 0xF4917C
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#define mmTPC5_CMDQ_CP_CURRENT_INST_HI 0xF49180
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#define mmTPC5_CMDQ_CP_BARRIER_CFG 0xF49184
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#define mmTPC5_CMDQ_CP_DBG_0 0xF49188
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#define mmTPC5_CMDQ_CQ_BUF_ADDR 0xF49308
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#define mmTPC5_CMDQ_CQ_BUF_RDATA 0xF4930C
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#endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */
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