/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_
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#define ASIC_REG_TPC4_CMDQ_REGS_H_
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/*
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*****************************************
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* TPC4_CMDQ (Prototype: CMDQ)
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*****************************************
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*/
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#define mmTPC4_CMDQ_GLBL_CFG0 0xF09000
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#define mmTPC4_CMDQ_GLBL_CFG1 0xF09004
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#define mmTPC4_CMDQ_GLBL_PROT 0xF09008
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#define mmTPC4_CMDQ_GLBL_ERR_CFG 0xF0900C
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#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO 0xF09010
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#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI 0xF09014
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#define mmTPC4_CMDQ_GLBL_ERR_WDATA 0xF09018
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#define mmTPC4_CMDQ_GLBL_SECURE_PROPS 0xF0901C
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#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS 0xF09020
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#define mmTPC4_CMDQ_GLBL_STS0 0xF09024
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#define mmTPC4_CMDQ_GLBL_STS1 0xF09028
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#define mmTPC4_CMDQ_CQ_CFG0 0xF090B0
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#define mmTPC4_CMDQ_CQ_CFG1 0xF090B4
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#define mmTPC4_CMDQ_CQ_ARUSER 0xF090B8
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#define mmTPC4_CMDQ_CQ_PTR_LO 0xF090C0
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#define mmTPC4_CMDQ_CQ_PTR_HI 0xF090C4
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#define mmTPC4_CMDQ_CQ_TSIZE 0xF090C8
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#define mmTPC4_CMDQ_CQ_CTL 0xF090CC
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#define mmTPC4_CMDQ_CQ_PTR_LO_STS 0xF090D4
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#define mmTPC4_CMDQ_CQ_PTR_HI_STS 0xF090D8
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#define mmTPC4_CMDQ_CQ_TSIZE_STS 0xF090DC
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#define mmTPC4_CMDQ_CQ_CTL_STS 0xF090E0
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#define mmTPC4_CMDQ_CQ_STS0 0xF090E4
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#define mmTPC4_CMDQ_CQ_STS1 0xF090E8
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#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN 0xF090F0
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#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF090F4
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#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT 0xF090F8
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#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF090FC
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#define mmTPC4_CMDQ_CQ_IFIFO_CNT 0xF09108
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#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF09120
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#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF09124
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#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF09128
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#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF0912C
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#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF09130
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#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF09134
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#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF09138
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#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF0913C
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#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF09140
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#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF09144
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#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF09148
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#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF0914C
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#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF09150
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#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF09154
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#define mmTPC4_CMDQ_CP_FENCE0_RDATA 0xF09158
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#define mmTPC4_CMDQ_CP_FENCE1_RDATA 0xF0915C
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#define mmTPC4_CMDQ_CP_FENCE2_RDATA 0xF09160
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#define mmTPC4_CMDQ_CP_FENCE3_RDATA 0xF09164
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#define mmTPC4_CMDQ_CP_FENCE0_CNT 0xF09168
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#define mmTPC4_CMDQ_CP_FENCE1_CNT 0xF0916C
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#define mmTPC4_CMDQ_CP_FENCE2_CNT 0xF09170
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#define mmTPC4_CMDQ_CP_FENCE3_CNT 0xF09174
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#define mmTPC4_CMDQ_CP_STS 0xF09178
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#define mmTPC4_CMDQ_CP_CURRENT_INST_LO 0xF0917C
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#define mmTPC4_CMDQ_CP_CURRENT_INST_HI 0xF09180
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#define mmTPC4_CMDQ_CP_BARRIER_CFG 0xF09184
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#define mmTPC4_CMDQ_CP_DBG_0 0xF09188
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#define mmTPC4_CMDQ_CQ_BUF_ADDR 0xF09308
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#define mmTPC4_CMDQ_CQ_BUF_RDATA 0xF0930C
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#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */
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