/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC2_CMDQ_REGS_H_
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#define ASIC_REG_TPC2_CMDQ_REGS_H_
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/*
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*****************************************
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* TPC2_CMDQ (Prototype: CMDQ)
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*****************************************
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*/
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#define mmTPC2_CMDQ_GLBL_CFG0 0xE89000
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#define mmTPC2_CMDQ_GLBL_CFG1 0xE89004
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#define mmTPC2_CMDQ_GLBL_PROT 0xE89008
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#define mmTPC2_CMDQ_GLBL_ERR_CFG 0xE8900C
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#define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO 0xE89010
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#define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI 0xE89014
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#define mmTPC2_CMDQ_GLBL_ERR_WDATA 0xE89018
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#define mmTPC2_CMDQ_GLBL_SECURE_PROPS 0xE8901C
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#define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS 0xE89020
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#define mmTPC2_CMDQ_GLBL_STS0 0xE89024
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#define mmTPC2_CMDQ_GLBL_STS1 0xE89028
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#define mmTPC2_CMDQ_CQ_CFG0 0xE890B0
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#define mmTPC2_CMDQ_CQ_CFG1 0xE890B4
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#define mmTPC2_CMDQ_CQ_ARUSER 0xE890B8
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#define mmTPC2_CMDQ_CQ_PTR_LO 0xE890C0
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#define mmTPC2_CMDQ_CQ_PTR_HI 0xE890C4
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#define mmTPC2_CMDQ_CQ_TSIZE 0xE890C8
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#define mmTPC2_CMDQ_CQ_CTL 0xE890CC
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#define mmTPC2_CMDQ_CQ_PTR_LO_STS 0xE890D4
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#define mmTPC2_CMDQ_CQ_PTR_HI_STS 0xE890D8
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#define mmTPC2_CMDQ_CQ_TSIZE_STS 0xE890DC
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#define mmTPC2_CMDQ_CQ_CTL_STS 0xE890E0
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#define mmTPC2_CMDQ_CQ_STS0 0xE890E4
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#define mmTPC2_CMDQ_CQ_STS1 0xE890E8
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#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN 0xE890F0
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#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE890F4
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#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT 0xE890F8
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#define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE890FC
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#define mmTPC2_CMDQ_CQ_IFIFO_CNT 0xE89108
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#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE89120
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#define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE89124
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#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE89128
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#define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE8912C
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#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE89130
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#define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE89134
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#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE89138
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#define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE8913C
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#define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE89140
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#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE89144
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#define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE89148
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#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE8914C
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#define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE89150
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#define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE89154
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#define mmTPC2_CMDQ_CP_FENCE0_RDATA 0xE89158
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#define mmTPC2_CMDQ_CP_FENCE1_RDATA 0xE8915C
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#define mmTPC2_CMDQ_CP_FENCE2_RDATA 0xE89160
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#define mmTPC2_CMDQ_CP_FENCE3_RDATA 0xE89164
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#define mmTPC2_CMDQ_CP_FENCE0_CNT 0xE89168
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#define mmTPC2_CMDQ_CP_FENCE1_CNT 0xE8916C
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#define mmTPC2_CMDQ_CP_FENCE2_CNT 0xE89170
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#define mmTPC2_CMDQ_CP_FENCE3_CNT 0xE89174
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#define mmTPC2_CMDQ_CP_STS 0xE89178
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#define mmTPC2_CMDQ_CP_CURRENT_INST_LO 0xE8917C
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#define mmTPC2_CMDQ_CP_CURRENT_INST_HI 0xE89180
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#define mmTPC2_CMDQ_CP_BARRIER_CFG 0xE89184
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#define mmTPC2_CMDQ_CP_DBG_0 0xE89188
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#define mmTPC2_CMDQ_CQ_BUF_ADDR 0xE89308
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#define mmTPC2_CMDQ_CQ_BUF_RDATA 0xE8930C
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#endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */
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