/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC1_CFG_REGS_H_
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#define ASIC_REG_TPC1_CFG_REGS_H_
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/*
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*****************************************
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* TPC1_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400
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#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404
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#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408
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#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE46418
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE4641C
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE46420
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE46424
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46428
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE4642C
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE46430
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46434
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE46438
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE4643C
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46440
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46444
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#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE46448
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#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE4644C
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#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE46450
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#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46454
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#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46458
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE4645C
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE46460
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE46464
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46468
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE4646C
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE46470
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46474
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE46478
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE4647C
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46480
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46484
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE46488
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE4648C
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE46490
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#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE46494
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#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46498
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#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE4649C
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#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE464A0
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#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE464A4
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE464A8
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE464AC
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE464B0
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE464B4
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE464B8
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE464BC
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE464C0
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE464C4
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE464C8
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE464CC
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE464D0
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE464D4
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464D8
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464DC
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#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE464E0
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#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464E4
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#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464E8
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#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464EC
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#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464F0
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464F4
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464F8
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE464FC
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE46500
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE46504
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE46508
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE4650C
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE46510
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE46514
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE46518
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE4651C
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE46520
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE46524
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE46528
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#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE4652C
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#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE46530
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#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE46534
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#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE46538
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#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE4653C
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE46540
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE46544
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE46548
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE4654C
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE46550
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE46554
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46558
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE4655C
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE46560
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46564
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE46568
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE4656C
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46570
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46574
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#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE46578
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#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE4657C
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#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE46580
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#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46584
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#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46588
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE4658C
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE46590
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE46594
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46598
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE4659C
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE465A0
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE465A4
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE465A8
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE465AC
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE465B0
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE465B4
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE465B8
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE465BC
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE465C0
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#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE465C4
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#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE465C8
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#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE465CC
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#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE465D0
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#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE465D4
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE465D8
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE465DC
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE465E0
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE465E4
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE465E8
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE465EC
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE465F0
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE465F4
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE465F8
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE465FC
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE46600
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE46604
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46608
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE4660C
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#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE46610
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#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46614
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#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE46618
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#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE4661C
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#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46620
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46624
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE46628
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE4662C
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE46630
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE46634
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE46638
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE4663C
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE46640
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE46644
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE46648
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE4664C
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE46650
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE46654
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE46658
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#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE4665C
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#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46660
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#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE46664
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#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46668
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#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE4666C
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#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46670
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#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE46674
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#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE46678
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#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE4667C
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#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE46680
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#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE46684
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#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE46688
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#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE4668C
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#define mmTPC1_CFG_KERNEL_SRF_0 0xE46690
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#define mmTPC1_CFG_KERNEL_SRF_1 0xE46694
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#define mmTPC1_CFG_KERNEL_SRF_2 0xE46698
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#define mmTPC1_CFG_KERNEL_SRF_3 0xE4669C
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#define mmTPC1_CFG_KERNEL_SRF_4 0xE466A0
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#define mmTPC1_CFG_KERNEL_SRF_5 0xE466A4
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#define mmTPC1_CFG_KERNEL_SRF_6 0xE466A8
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#define mmTPC1_CFG_KERNEL_SRF_7 0xE466AC
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#define mmTPC1_CFG_KERNEL_SRF_8 0xE466B0
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#define mmTPC1_CFG_KERNEL_SRF_9 0xE466B4
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#define mmTPC1_CFG_KERNEL_SRF_10 0xE466B8
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#define mmTPC1_CFG_KERNEL_SRF_11 0xE466BC
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#define mmTPC1_CFG_KERNEL_SRF_12 0xE466C0
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#define mmTPC1_CFG_KERNEL_SRF_13 0xE466C4
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#define mmTPC1_CFG_KERNEL_SRF_14 0xE466C8
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#define mmTPC1_CFG_KERNEL_SRF_15 0xE466CC
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#define mmTPC1_CFG_KERNEL_SRF_16 0xE466D0
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#define mmTPC1_CFG_KERNEL_SRF_17 0xE466D4
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#define mmTPC1_CFG_KERNEL_SRF_18 0xE466D8
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#define mmTPC1_CFG_KERNEL_SRF_19 0xE466DC
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#define mmTPC1_CFG_KERNEL_SRF_20 0xE466E0
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#define mmTPC1_CFG_KERNEL_SRF_21 0xE466E4
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#define mmTPC1_CFG_KERNEL_SRF_22 0xE466E8
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#define mmTPC1_CFG_KERNEL_SRF_23 0xE466EC
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#define mmTPC1_CFG_KERNEL_SRF_24 0xE466F0
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#define mmTPC1_CFG_KERNEL_SRF_25 0xE466F4
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#define mmTPC1_CFG_KERNEL_SRF_26 0xE466F8
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#define mmTPC1_CFG_KERNEL_SRF_27 0xE466FC
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#define mmTPC1_CFG_KERNEL_SRF_28 0xE46700
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#define mmTPC1_CFG_KERNEL_SRF_29 0xE46704
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#define mmTPC1_CFG_KERNEL_SRF_30 0xE46708
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#define mmTPC1_CFG_KERNEL_SRF_31 0xE4670C
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#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE46710
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#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46714
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#define mmTPC1_CFG_RESERVED_DESC_END 0xE46738
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#define mmTPC1_CFG_ROUND_CSR 0xE467FC
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#define mmTPC1_CFG_TBUF_BASE_ADDR_LOW 0xE46800
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#define mmTPC1_CFG_TBUF_BASE_ADDR_HIGH 0xE46804
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#define mmTPC1_CFG_SEMAPHORE 0xE46808
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#define mmTPC1_CFG_VFLAGS 0xE4680C
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#define mmTPC1_CFG_SFLAGS 0xE46810
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#define mmTPC1_CFG_LFSR_POLYNOM 0xE46818
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#define mmTPC1_CFG_STATUS 0xE4681C
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#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46820
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#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46824
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#define mmTPC1_CFG_SM_BASE_ADDRESS_LOW 0xE46828
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#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4682C
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#define mmTPC1_CFG_TPC_CMD 0xE46830
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#define mmTPC1_CFG_TPC_EXECUTE 0xE46838
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#define mmTPC1_CFG_TPC_STALL 0xE4683C
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#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46840
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#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46844
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#define mmTPC1_CFG_MSS_CONFIG 0xE46854
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#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46858
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#define mmTPC1_CFG_TPC_INTR_MASK 0xE4685C
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#define mmTPC1_CFG_TSB_CONFIG 0xE46860
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#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00
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#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04
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#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08
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#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE46A18
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A1C
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A20
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE46A24
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A28
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A2C
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE46A30
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A34
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A38
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE46A3C
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A40
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A44
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#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE46A48
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#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A4C
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#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A50
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#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A54
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#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A58
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A5C
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A60
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE46A64
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A68
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A6C
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE46A70
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A74
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A78
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE46A7C
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A80
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A84
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE46A88
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A8C
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A90
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#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE46A94
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#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A98
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#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A9C
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#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46AA0
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#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46AA4
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46AA8
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46AAC
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE46AB0
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46AB4
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46AB8
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE46ABC
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46AC0
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46AC4
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE46AC8
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46ACC
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46AD0
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE46AD4
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AD8
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46ADC
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#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE46AE0
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#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AE4
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#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AE8
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#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AEC
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#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AF0
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AF4
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46AF8
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE46AFC
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46B00
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46B04
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE46B08
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46B0C
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46B10
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE46B14
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46B18
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46B1C
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE46B20
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46B24
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46B28
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#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE46B2C
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#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46B30
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#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46B34
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#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46B38
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#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46B3C
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46B40
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46B44
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE46B48
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46B4C
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46B50
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE46B54
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B58
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B5C
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE46B60
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B64
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B68
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE46B6C
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B70
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B74
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#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE46B78
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#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B7C
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#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B80
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#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B84
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#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B88
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B8C
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B90
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE46B94
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B98
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B9C
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE46BA0
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46BA4
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46BA8
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE46BAC
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46BB0
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46BB4
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE46BB8
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46BBC
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46BC0
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#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE46BC4
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#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46BC8
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#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46BCC
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#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46BD0
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#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46BD4
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46BD8
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46BDC
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE46BE0
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46BE4
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46BE8
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE46BEC
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46BF0
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46BF4
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE46BF8
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46BFC
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46C00
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE46C04
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46C08
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46C0C
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#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE46C10
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#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46C14
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#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46C18
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#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46C1C
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#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46C20
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46C24
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46C28
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE46C2C
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46C30
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46C34
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE46C38
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46C3C
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46C40
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE46C44
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46C48
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46C4C
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE46C50
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46C54
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46C58
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#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE46C5C
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#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46C60
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#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46C64
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#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46C68
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#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46C6C
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#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46C70
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#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46C74
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#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46C78
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#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46C7C
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#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46C80
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#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46C84
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#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46C88
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#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46C8C
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#define mmTPC1_CFG_QM_SRF_0 0xE46C90
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#define mmTPC1_CFG_QM_SRF_1 0xE46C94
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#define mmTPC1_CFG_QM_SRF_2 0xE46C98
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#define mmTPC1_CFG_QM_SRF_3 0xE46C9C
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#define mmTPC1_CFG_QM_SRF_4 0xE46CA0
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#define mmTPC1_CFG_QM_SRF_5 0xE46CA4
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#define mmTPC1_CFG_QM_SRF_6 0xE46CA8
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#define mmTPC1_CFG_QM_SRF_7 0xE46CAC
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#define mmTPC1_CFG_QM_SRF_8 0xE46CB0
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#define mmTPC1_CFG_QM_SRF_9 0xE46CB4
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#define mmTPC1_CFG_QM_SRF_10 0xE46CB8
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#define mmTPC1_CFG_QM_SRF_11 0xE46CBC
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#define mmTPC1_CFG_QM_SRF_12 0xE46CC0
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#define mmTPC1_CFG_QM_SRF_13 0xE46CC4
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#define mmTPC1_CFG_QM_SRF_14 0xE46CC8
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#define mmTPC1_CFG_QM_SRF_15 0xE46CCC
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#define mmTPC1_CFG_QM_SRF_16 0xE46CD0
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#define mmTPC1_CFG_QM_SRF_17 0xE46CD4
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#define mmTPC1_CFG_QM_SRF_18 0xE46CD8
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#define mmTPC1_CFG_QM_SRF_19 0xE46CDC
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#define mmTPC1_CFG_QM_SRF_20 0xE46CE0
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#define mmTPC1_CFG_QM_SRF_21 0xE46CE4
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#define mmTPC1_CFG_QM_SRF_22 0xE46CE8
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#define mmTPC1_CFG_QM_SRF_23 0xE46CEC
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#define mmTPC1_CFG_QM_SRF_24 0xE46CF0
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#define mmTPC1_CFG_QM_SRF_25 0xE46CF4
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#define mmTPC1_CFG_QM_SRF_26 0xE46CF8
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#define mmTPC1_CFG_QM_SRF_27 0xE46CFC
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#define mmTPC1_CFG_QM_SRF_28 0xE46D00
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#define mmTPC1_CFG_QM_SRF_29 0xE46D04
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#define mmTPC1_CFG_QM_SRF_30 0xE46D08
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#define mmTPC1_CFG_QM_SRF_31 0xE46D0C
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#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46D10
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#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D14
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#define mmTPC1_CFG_ARUSER 0xE46D18
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#define mmTPC1_CFG_AWUSER 0xE46D1C
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#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE46E00
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#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE46E04
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#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE46E08
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#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE46E0C
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#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE46E10
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#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE46E14
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#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE46E18
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#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE46E1C
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#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE46E20
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#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE46E24
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#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE46E28
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#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE46E2C
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#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */
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