/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC0_QM_REGS_H_
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#define ASIC_REG_TPC0_QM_REGS_H_
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/*
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*****************************************
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* TPC0_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC0_QM_GLBL_CFG0 0xE08000
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#define mmTPC0_QM_GLBL_CFG1 0xE08004
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#define mmTPC0_QM_GLBL_PROT 0xE08008
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#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C
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#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08010
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#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08014
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#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08018
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#define mmTPC0_QM_GLBL_SECURE_PROPS 0xE0801C
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS 0xE08020
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#define mmTPC0_QM_GLBL_STS0 0xE08024
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#define mmTPC0_QM_GLBL_STS1 0xE08028
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#define mmTPC0_QM_PQ_BASE_LO 0xE08060
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#define mmTPC0_QM_PQ_BASE_HI 0xE08064
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#define mmTPC0_QM_PQ_SIZE 0xE08068
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#define mmTPC0_QM_PQ_PI 0xE0806C
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#define mmTPC0_QM_PQ_CI 0xE08070
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#define mmTPC0_QM_PQ_CFG0 0xE08074
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#define mmTPC0_QM_PQ_CFG1 0xE08078
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#define mmTPC0_QM_PQ_ARUSER 0xE0807C
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#define mmTPC0_QM_PQ_PUSH0 0xE08080
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#define mmTPC0_QM_PQ_PUSH1 0xE08084
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#define mmTPC0_QM_PQ_PUSH2 0xE08088
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#define mmTPC0_QM_PQ_PUSH3 0xE0808C
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#define mmTPC0_QM_PQ_STS0 0xE08090
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#define mmTPC0_QM_PQ_STS1 0xE08094
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#define mmTPC0_QM_PQ_RD_RATE_LIM_EN 0xE080A0
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#define mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xE080A4
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#define mmTPC0_QM_PQ_RD_RATE_LIM_SAT 0xE080A8
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#define mmTPC0_QM_PQ_RD_RATE_LIM_TOUT 0xE080AC
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#define mmTPC0_QM_CQ_CFG0 0xE080B0
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#define mmTPC0_QM_CQ_CFG1 0xE080B4
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#define mmTPC0_QM_CQ_ARUSER 0xE080B8
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#define mmTPC0_QM_CQ_PTR_LO 0xE080C0
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#define mmTPC0_QM_CQ_PTR_HI 0xE080C4
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#define mmTPC0_QM_CQ_TSIZE 0xE080C8
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#define mmTPC0_QM_CQ_CTL 0xE080CC
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#define mmTPC0_QM_CQ_PTR_LO_STS 0xE080D4
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#define mmTPC0_QM_CQ_PTR_HI_STS 0xE080D8
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#define mmTPC0_QM_CQ_TSIZE_STS 0xE080DC
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#define mmTPC0_QM_CQ_CTL_STS 0xE080E0
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#define mmTPC0_QM_CQ_STS0 0xE080E4
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#define mmTPC0_QM_CQ_STS1 0xE080E8
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#define mmTPC0_QM_CQ_RD_RATE_LIM_EN 0xE080F0
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#define mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xE080F4
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#define mmTPC0_QM_CQ_RD_RATE_LIM_SAT 0xE080F8
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#define mmTPC0_QM_CQ_RD_RATE_LIM_TOUT 0xE080FC
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#define mmTPC0_QM_CQ_IFIFO_CNT 0xE08108
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO 0xE08120
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI 0xE08124
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO 0xE08128
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI 0xE0812C
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO 0xE08130
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI 0xE08134
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO 0xE08138
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI 0xE0813C
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET 0xE08140
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xE08144
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xE08148
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xE0814C
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#define mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xE08150
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#define mmTPC0_QM_CP_LDMA_COMMIT_OFFSET 0xE08154
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#define mmTPC0_QM_CP_FENCE0_RDATA 0xE08158
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#define mmTPC0_QM_CP_FENCE1_RDATA 0xE0815C
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#define mmTPC0_QM_CP_FENCE2_RDATA 0xE08160
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#define mmTPC0_QM_CP_FENCE3_RDATA 0xE08164
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#define mmTPC0_QM_CP_FENCE0_CNT 0xE08168
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#define mmTPC0_QM_CP_FENCE1_CNT 0xE0816C
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#define mmTPC0_QM_CP_FENCE2_CNT 0xE08170
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#define mmTPC0_QM_CP_FENCE3_CNT 0xE08174
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#define mmTPC0_QM_CP_STS 0xE08178
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#define mmTPC0_QM_CP_CURRENT_INST_LO 0xE0817C
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#define mmTPC0_QM_CP_CURRENT_INST_HI 0xE08180
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#define mmTPC0_QM_CP_BARRIER_CFG 0xE08184
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#define mmTPC0_QM_CP_DBG_0 0xE08188
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#define mmTPC0_QM_PQ_BUF_ADDR 0xE08300
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#define mmTPC0_QM_PQ_BUF_RDATA 0xE08304
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#define mmTPC0_QM_CQ_BUF_ADDR 0xE08308
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#define mmTPC0_QM_CQ_BUF_RDATA 0xE0830C
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#endif /* ASIC_REG_TPC0_QM_REGS_H_ */
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