/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC0_NRTR_REGS_H_
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#define ASIC_REG_TPC0_NRTR_REGS_H_
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/*
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*****************************************
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* TPC0_NRTR (Prototype: IF_NRTR)
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*****************************************
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*/
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#define mmTPC0_NRTR_HBW_MAX_CRED 0xE00100
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#define mmTPC0_NRTR_LBW_MAX_CRED 0xE00120
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#define mmTPC0_NRTR_DBG_E_ARB 0xE00300
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#define mmTPC0_NRTR_DBG_W_ARB 0xE00304
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#define mmTPC0_NRTR_DBG_N_ARB 0xE00308
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#define mmTPC0_NRTR_DBG_S_ARB 0xE0030C
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#define mmTPC0_NRTR_DBG_L_ARB 0xE00310
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#define mmTPC0_NRTR_DBG_E_ARB_MAX 0xE00320
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#define mmTPC0_NRTR_DBG_W_ARB_MAX 0xE00324
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#define mmTPC0_NRTR_DBG_N_ARB_MAX 0xE00328
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#define mmTPC0_NRTR_DBG_S_ARB_MAX 0xE0032C
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#define mmTPC0_NRTR_DBG_L_ARB_MAX 0xE00330
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#define mmTPC0_NRTR_SPLIT_COEF_0 0xE00400
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#define mmTPC0_NRTR_SPLIT_COEF_1 0xE00404
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#define mmTPC0_NRTR_SPLIT_COEF_2 0xE00408
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#define mmTPC0_NRTR_SPLIT_COEF_3 0xE0040C
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#define mmTPC0_NRTR_SPLIT_COEF_4 0xE00410
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#define mmTPC0_NRTR_SPLIT_COEF_5 0xE00414
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#define mmTPC0_NRTR_SPLIT_COEF_6 0xE00418
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#define mmTPC0_NRTR_SPLIT_COEF_7 0xE0041C
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#define mmTPC0_NRTR_SPLIT_COEF_8 0xE00420
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#define mmTPC0_NRTR_SPLIT_COEF_9 0xE00424
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#define mmTPC0_NRTR_SPLIT_CFG 0xE00440
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#define mmTPC0_NRTR_SPLIT_RD_SAT 0xE00444
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#define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN 0xE00448
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#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0 0xE0044C
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#define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1 0xE00450
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#define mmTPC0_NRTR_SPLIT_WR_SAT 0xE00454
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#define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN 0xE00458
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#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0 0xE0045C
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#define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1 0xE00460
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#define mmTPC0_NRTR_HBW_RANGE_HIT 0xE00470
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_0 0xE00480
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_1 0xE00484
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_2 0xE00488
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_3 0xE0048C
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_4 0xE00490
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_5 0xE00494
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_6 0xE00498
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#define mmTPC0_NRTR_HBW_RANGE_MASK_L_7 0xE0049C
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_0 0xE004A0
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_1 0xE004A4
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_2 0xE004A8
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_3 0xE004AC
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_4 0xE004B0
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_5 0xE004B4
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_6 0xE004B8
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#define mmTPC0_NRTR_HBW_RANGE_MASK_H_7 0xE004BC
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_0 0xE004C0
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_1 0xE004C4
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_2 0xE004C8
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_3 0xE004CC
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_4 0xE004D0
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_5 0xE004D4
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_6 0xE004D8
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#define mmTPC0_NRTR_HBW_RANGE_BASE_L_7 0xE004DC
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_0 0xE004E0
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_1 0xE004E4
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_2 0xE004E8
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_3 0xE004EC
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_4 0xE004F0
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_5 0xE004F4
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_6 0xE004F8
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#define mmTPC0_NRTR_HBW_RANGE_BASE_H_7 0xE004FC
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#define mmTPC0_NRTR_LBW_RANGE_HIT 0xE00500
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#define mmTPC0_NRTR_LBW_RANGE_MASK_0 0xE00510
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#define mmTPC0_NRTR_LBW_RANGE_MASK_1 0xE00514
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#define mmTPC0_NRTR_LBW_RANGE_MASK_2 0xE00518
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#define mmTPC0_NRTR_LBW_RANGE_MASK_3 0xE0051C
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#define mmTPC0_NRTR_LBW_RANGE_MASK_4 0xE00520
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#define mmTPC0_NRTR_LBW_RANGE_MASK_5 0xE00524
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#define mmTPC0_NRTR_LBW_RANGE_MASK_6 0xE00528
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#define mmTPC0_NRTR_LBW_RANGE_MASK_7 0xE0052C
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#define mmTPC0_NRTR_LBW_RANGE_MASK_8 0xE00530
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#define mmTPC0_NRTR_LBW_RANGE_MASK_9 0xE00534
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#define mmTPC0_NRTR_LBW_RANGE_MASK_10 0xE00538
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#define mmTPC0_NRTR_LBW_RANGE_MASK_11 0xE0053C
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#define mmTPC0_NRTR_LBW_RANGE_MASK_12 0xE00540
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#define mmTPC0_NRTR_LBW_RANGE_MASK_13 0xE00544
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#define mmTPC0_NRTR_LBW_RANGE_MASK_14 0xE00548
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#define mmTPC0_NRTR_LBW_RANGE_MASK_15 0xE0054C
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#define mmTPC0_NRTR_LBW_RANGE_BASE_0 0xE00550
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#define mmTPC0_NRTR_LBW_RANGE_BASE_1 0xE00554
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#define mmTPC0_NRTR_LBW_RANGE_BASE_2 0xE00558
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#define mmTPC0_NRTR_LBW_RANGE_BASE_3 0xE0055C
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#define mmTPC0_NRTR_LBW_RANGE_BASE_4 0xE00560
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#define mmTPC0_NRTR_LBW_RANGE_BASE_5 0xE00564
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#define mmTPC0_NRTR_LBW_RANGE_BASE_6 0xE00568
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#define mmTPC0_NRTR_LBW_RANGE_BASE_7 0xE0056C
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#define mmTPC0_NRTR_LBW_RANGE_BASE_8 0xE00570
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#define mmTPC0_NRTR_LBW_RANGE_BASE_9 0xE00574
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#define mmTPC0_NRTR_LBW_RANGE_BASE_10 0xE00578
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#define mmTPC0_NRTR_LBW_RANGE_BASE_11 0xE0057C
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#define mmTPC0_NRTR_LBW_RANGE_BASE_12 0xE00580
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#define mmTPC0_NRTR_LBW_RANGE_BASE_13 0xE00584
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#define mmTPC0_NRTR_LBW_RANGE_BASE_14 0xE00588
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#define mmTPC0_NRTR_LBW_RANGE_BASE_15 0xE0058C
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#define mmTPC0_NRTR_RGLTR 0xE00590
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#define mmTPC0_NRTR_RGLTR_WR_RESULT 0xE00594
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#define mmTPC0_NRTR_RGLTR_RD_RESULT 0xE00598
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#define mmTPC0_NRTR_SCRAMB_EN 0xE00600
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#define mmTPC0_NRTR_NON_LIN_SCRAMB 0xE00604
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#endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */
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