/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC0_CMDQ_REGS_H_
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#define ASIC_REG_TPC0_CMDQ_REGS_H_
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/*
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*****************************************
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* TPC0_CMDQ (Prototype: CMDQ)
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*****************************************
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*/
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#define mmTPC0_CMDQ_GLBL_CFG0 0xE09000
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#define mmTPC0_CMDQ_GLBL_CFG1 0xE09004
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#define mmTPC0_CMDQ_GLBL_PROT 0xE09008
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#define mmTPC0_CMDQ_GLBL_ERR_CFG 0xE0900C
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#define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO 0xE09010
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#define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI 0xE09014
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#define mmTPC0_CMDQ_GLBL_ERR_WDATA 0xE09018
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#define mmTPC0_CMDQ_GLBL_SECURE_PROPS 0xE0901C
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#define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS 0xE09020
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#define mmTPC0_CMDQ_GLBL_STS0 0xE09024
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#define mmTPC0_CMDQ_GLBL_STS1 0xE09028
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#define mmTPC0_CMDQ_CQ_CFG0 0xE090B0
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#define mmTPC0_CMDQ_CQ_CFG1 0xE090B4
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#define mmTPC0_CMDQ_CQ_ARUSER 0xE090B8
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#define mmTPC0_CMDQ_CQ_PTR_LO 0xE090C0
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#define mmTPC0_CMDQ_CQ_PTR_HI 0xE090C4
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#define mmTPC0_CMDQ_CQ_TSIZE 0xE090C8
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#define mmTPC0_CMDQ_CQ_CTL 0xE090CC
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#define mmTPC0_CMDQ_CQ_PTR_LO_STS 0xE090D4
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#define mmTPC0_CMDQ_CQ_PTR_HI_STS 0xE090D8
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#define mmTPC0_CMDQ_CQ_TSIZE_STS 0xE090DC
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#define mmTPC0_CMDQ_CQ_CTL_STS 0xE090E0
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#define mmTPC0_CMDQ_CQ_STS0 0xE090E4
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#define mmTPC0_CMDQ_CQ_STS1 0xE090E8
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#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN 0xE090F0
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#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE090F4
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#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT 0xE090F8
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#define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE090FC
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#define mmTPC0_CMDQ_CQ_IFIFO_CNT 0xE09108
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#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE09120
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#define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE09124
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#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE09128
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#define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE0912C
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#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE09130
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#define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE09134
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#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE09138
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#define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE0913C
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#define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE09140
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#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE09144
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#define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE09148
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#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE0914C
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#define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE09150
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#define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE09154
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#define mmTPC0_CMDQ_CP_FENCE0_RDATA 0xE09158
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#define mmTPC0_CMDQ_CP_FENCE1_RDATA 0xE0915C
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#define mmTPC0_CMDQ_CP_FENCE2_RDATA 0xE09160
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#define mmTPC0_CMDQ_CP_FENCE3_RDATA 0xE09164
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#define mmTPC0_CMDQ_CP_FENCE0_CNT 0xE09168
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#define mmTPC0_CMDQ_CP_FENCE1_CNT 0xE0916C
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#define mmTPC0_CMDQ_CP_FENCE2_CNT 0xE09170
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#define mmTPC0_CMDQ_CP_FENCE3_CNT 0xE09174
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#define mmTPC0_CMDQ_CP_STS 0xE09178
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#define mmTPC0_CMDQ_CP_CURRENT_INST_LO 0xE0917C
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#define mmTPC0_CMDQ_CP_CURRENT_INST_HI 0xE09180
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#define mmTPC0_CMDQ_CP_BARRIER_CFG 0xE09184
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#define mmTPC0_CMDQ_CP_DBG_0 0xE09188
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#define mmTPC0_CMDQ_CQ_BUF_ADDR 0xE09308
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#define mmTPC0_CMDQ_CQ_BUF_RDATA 0xE0930C
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#endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */
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