/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_
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#define ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_
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/*
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*****************************************
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* SRAM_Y0_X1_RTR (Prototype: IC_RTR)
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*****************************************
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*/
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#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_E_ARB 0x205100
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#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_W_ARB 0x205104
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#define mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB 0x205110
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#define mmSRAM_Y0_X1_RTR_HBW_E_ARB_MAX 0x205120
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#define mmSRAM_Y0_X1_RTR_HBW_W_ARB_MAX 0x205124
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#define mmSRAM_Y0_X1_RTR_HBW_L_ARB_MAX 0x205130
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#define mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB 0x205140
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#define mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB 0x205144
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#define mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB 0x205148
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#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB 0x205160
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#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB 0x205164
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#define mmSRAM_Y0_X1_RTR_HBW_WR_RS_L_ARB 0x205168
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#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_E_ARB 0x205200
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#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_W_ARB 0x205204
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#define mmSRAM_Y0_X1_RTR_LBW_RD_RQ_L_ARB 0x205210
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#define mmSRAM_Y0_X1_RTR_LBW_E_ARB_MAX 0x205220
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#define mmSRAM_Y0_X1_RTR_LBW_W_ARB_MAX 0x205224
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#define mmSRAM_Y0_X1_RTR_LBW_L_ARB_MAX 0x205230
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#define mmSRAM_Y0_X1_RTR_LBW_DATA_E_ARB 0x205240
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#define mmSRAM_Y0_X1_RTR_LBW_DATA_W_ARB 0x205244
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#define mmSRAM_Y0_X1_RTR_LBW_DATA_L_ARB 0x205248
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#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_E_ARB 0x205260
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#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_W_ARB 0x205264
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#define mmSRAM_Y0_X1_RTR_LBW_WR_RS_L_ARB 0x205268
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#define mmSRAM_Y0_X1_RTR_DBG_E_ARB 0x205300
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#define mmSRAM_Y0_X1_RTR_DBG_W_ARB 0x205304
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#define mmSRAM_Y0_X1_RTR_DBG_L_ARB 0x205310
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#define mmSRAM_Y0_X1_RTR_DBG_E_ARB_MAX 0x205320
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#define mmSRAM_Y0_X1_RTR_DBG_W_ARB_MAX 0x205324
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#define mmSRAM_Y0_X1_RTR_DBG_L_ARB_MAX 0x205330
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#endif /* ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_ */
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