/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_
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#define ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_
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/*
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*****************************************
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* SRAM_Y0_X0_RTR (Prototype: IC_RTR)
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*****************************************
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*/
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#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_E_ARB 0x201100
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#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_W_ARB 0x201104
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#define mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB 0x201110
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#define mmSRAM_Y0_X0_RTR_HBW_E_ARB_MAX 0x201120
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#define mmSRAM_Y0_X0_RTR_HBW_W_ARB_MAX 0x201124
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#define mmSRAM_Y0_X0_RTR_HBW_L_ARB_MAX 0x201130
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#define mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB 0x201140
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#define mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB 0x201144
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#define mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB 0x201148
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#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB 0x201160
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#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB 0x201164
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#define mmSRAM_Y0_X0_RTR_HBW_WR_RS_L_ARB 0x201168
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#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_E_ARB 0x201200
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#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_W_ARB 0x201204
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#define mmSRAM_Y0_X0_RTR_LBW_RD_RQ_L_ARB 0x201210
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#define mmSRAM_Y0_X0_RTR_LBW_E_ARB_MAX 0x201220
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#define mmSRAM_Y0_X0_RTR_LBW_W_ARB_MAX 0x201224
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#define mmSRAM_Y0_X0_RTR_LBW_L_ARB_MAX 0x201230
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#define mmSRAM_Y0_X0_RTR_LBW_DATA_E_ARB 0x201240
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#define mmSRAM_Y0_X0_RTR_LBW_DATA_W_ARB 0x201244
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#define mmSRAM_Y0_X0_RTR_LBW_DATA_L_ARB 0x201248
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#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_E_ARB 0x201260
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#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_W_ARB 0x201264
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#define mmSRAM_Y0_X0_RTR_LBW_WR_RS_L_ARB 0x201268
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#define mmSRAM_Y0_X0_RTR_DBG_E_ARB 0x201300
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#define mmSRAM_Y0_X0_RTR_DBG_W_ARB 0x201304
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#define mmSRAM_Y0_X0_RTR_DBG_L_ARB 0x201310
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#define mmSRAM_Y0_X0_RTR_DBG_E_ARB_MAX 0x201320
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#define mmSRAM_Y0_X0_RTR_DBG_W_ARB_MAX 0x201324
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#define mmSRAM_Y0_X0_RTR_DBG_L_ARB_MAX 0x201330
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#endif /* ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_ */
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