/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_
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#define ASIC_REG_PSOC_MME_PLL_REGS_H_
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/*
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*****************************************
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* PSOC_MME_PLL (Prototype: PLL)
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*****************************************
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*/
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#define mmPSOC_MME_PLL_NR 0xC71100
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#define mmPSOC_MME_PLL_NF 0xC71104
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#define mmPSOC_MME_PLL_OD 0xC71108
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#define mmPSOC_MME_PLL_NB 0xC7110C
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#define mmPSOC_MME_PLL_CFG 0xC71110
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#define mmPSOC_MME_PLL_LOSE_MASK 0xC71120
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#define mmPSOC_MME_PLL_LOCK_INTR 0xC71128
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#define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C
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#define mmPSOC_MME_PLL_DATA_CHNG 0xC71130
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#define mmPSOC_MME_PLL_RST 0xC71134
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#define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150
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#define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200
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#define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204
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#define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208
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#define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C
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#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220
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#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224
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#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228
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#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C
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#define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280
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#define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284
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#define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288
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#define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C
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#define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0
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#define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4
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#define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8
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#define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC
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#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0
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#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4
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#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8
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#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC
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#define mmPSOC_MME_PLL_CLK_GATER 0xC71300
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#define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310
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#define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314
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#define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318
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#define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C
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#define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400
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#define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410
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#define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420
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#define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430
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#define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440
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#endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */
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