/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PSOC_ETR_REGS_H_
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#define ASIC_REG_PSOC_ETR_REGS_H_
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/*
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*****************************************
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* PSOC_ETR (Prototype: ETR)
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*****************************************
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*/
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#define mmPSOC_ETR_RSZ 0x2C43004
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#define mmPSOC_ETR_STS 0x2C4300C
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#define mmPSOC_ETR_RRD 0x2C43010
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#define mmPSOC_ETR_RRP 0x2C43014
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#define mmPSOC_ETR_RWP 0x2C43018
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#define mmPSOC_ETR_TRG 0x2C4301C
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#define mmPSOC_ETR_CTL 0x2C43020
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#define mmPSOC_ETR_RWD 0x2C43024
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#define mmPSOC_ETR_MODE 0x2C43028
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#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C
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#define mmPSOC_ETR_CBUFLEVEL 0x2C43030
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#define mmPSOC_ETR_BUFWM 0x2C43034
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#define mmPSOC_ETR_RRPHI 0x2C43038
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#define mmPSOC_ETR_RWPHI 0x2C4303C
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#define mmPSOC_ETR_AXICTL 0x2C43110
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#define mmPSOC_ETR_DBALO 0x2C43118
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#define mmPSOC_ETR_DBAHI 0x2C4311C
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#define mmPSOC_ETR_FFSR 0x2C43300
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#define mmPSOC_ETR_FFCR 0x2C43304
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#define mmPSOC_ETR_PSCR 0x2C43308
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#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0
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#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8
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#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC
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#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0
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#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4
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#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8
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#define mmPSOC_ETR_ITCTRL 0x2C43F00
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#define mmPSOC_ETR_CLAIMSET 0x2C43FA0
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#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4
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#define mmPSOC_ETR_LAR 0x2C43FB0
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#define mmPSOC_ETR_LSR 0x2C43FB4
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#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8
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#define mmPSOC_ETR_DEVID 0x2C43FC8
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#define mmPSOC_ETR_DEVTYPE 0x2C43FCC
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#define mmPSOC_ETR_PERIPHID4 0x2C43FD0
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#define mmPSOC_ETR_PERIPHID5 0x2C43FD4
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#define mmPSOC_ETR_PERIPHID6 0x2C43FD8
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#define mmPSOC_ETR_PERIPHID7 0x2C43FDC
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#define mmPSOC_ETR_PERIPHID0 0x2C43FE0
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#define mmPSOC_ETR_PERIPHID1 0x2C43FE4
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#define mmPSOC_ETR_PERIPHID2 0x2C43FE8
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#define mmPSOC_ETR_PERIPHID3 0x2C43FEC
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#define mmPSOC_ETR_COMPID0 0x2C43FF0
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#define mmPSOC_ETR_COMPID1 0x2C43FF4
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#define mmPSOC_ETR_COMPID2 0x2C43FF8
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#define mmPSOC_ETR_COMPID3 0x2C43FFC
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#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */
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