/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PCI_NRTR_REGS_H_
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#define ASIC_REG_PCI_NRTR_REGS_H_
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/*
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*****************************************
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* PCI_NRTR (Prototype: IF_NRTR)
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*****************************************
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*/
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#define mmPCI_NRTR_HBW_MAX_CRED 0x100
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#define mmPCI_NRTR_LBW_MAX_CRED 0x120
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#define mmPCI_NRTR_DBG_E_ARB 0x300
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#define mmPCI_NRTR_DBG_W_ARB 0x304
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#define mmPCI_NRTR_DBG_N_ARB 0x308
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#define mmPCI_NRTR_DBG_S_ARB 0x30C
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#define mmPCI_NRTR_DBG_L_ARB 0x310
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#define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
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#define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
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#define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
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#define mmPCI_NRTR_DBG_S_ARB_MAX 0x32C
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#define mmPCI_NRTR_DBG_L_ARB_MAX 0x330
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#define mmPCI_NRTR_SPLIT_COEF_0 0x400
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#define mmPCI_NRTR_SPLIT_COEF_1 0x404
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#define mmPCI_NRTR_SPLIT_COEF_2 0x408
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#define mmPCI_NRTR_SPLIT_COEF_3 0x40C
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#define mmPCI_NRTR_SPLIT_COEF_4 0x410
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#define mmPCI_NRTR_SPLIT_COEF_5 0x414
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#define mmPCI_NRTR_SPLIT_COEF_6 0x418
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#define mmPCI_NRTR_SPLIT_COEF_7 0x41C
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#define mmPCI_NRTR_SPLIT_COEF_8 0x420
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#define mmPCI_NRTR_SPLIT_COEF_9 0x424
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#define mmPCI_NRTR_SPLIT_CFG 0x440
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#define mmPCI_NRTR_SPLIT_RD_SAT 0x444
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#define mmPCI_NRTR_SPLIT_RD_RST_TOKEN 0x448
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#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0 0x44C
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#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1 0x450
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#define mmPCI_NRTR_SPLIT_WR_SAT 0x454
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#define mmPCI_NRTR_WPLIT_WR_TST_TOLEN 0x458
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#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0 0x45C
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#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1 0x460
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#define mmPCI_NRTR_HBW_RANGE_HIT 0x470
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_0 0x480
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_1 0x484
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_2 0x488
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_3 0x48C
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_4 0x490
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_5 0x494
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_6 0x498
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#define mmPCI_NRTR_HBW_RANGE_MASK_L_7 0x49C
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_0 0x4A0
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_1 0x4A4
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_2 0x4A8
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_3 0x4AC
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_4 0x4B0
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_5 0x4B4
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_6 0x4B8
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#define mmPCI_NRTR_HBW_RANGE_MASK_H_7 0x4BC
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_0 0x4C0
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_1 0x4C4
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_2 0x4C8
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_3 0x4CC
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_4 0x4D0
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_5 0x4D4
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_6 0x4D8
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#define mmPCI_NRTR_HBW_RANGE_BASE_L_7 0x4DC
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_0 0x4E0
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_1 0x4E4
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_2 0x4E8
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_3 0x4EC
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_4 0x4F0
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_5 0x4F4
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_6 0x4F8
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#define mmPCI_NRTR_HBW_RANGE_BASE_H_7 0x4FC
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#define mmPCI_NRTR_LBW_RANGE_HIT 0x500
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#define mmPCI_NRTR_LBW_RANGE_MASK_0 0x510
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#define mmPCI_NRTR_LBW_RANGE_MASK_1 0x514
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#define mmPCI_NRTR_LBW_RANGE_MASK_2 0x518
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#define mmPCI_NRTR_LBW_RANGE_MASK_3 0x51C
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#define mmPCI_NRTR_LBW_RANGE_MASK_4 0x520
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#define mmPCI_NRTR_LBW_RANGE_MASK_5 0x524
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#define mmPCI_NRTR_LBW_RANGE_MASK_6 0x528
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#define mmPCI_NRTR_LBW_RANGE_MASK_7 0x52C
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#define mmPCI_NRTR_LBW_RANGE_MASK_8 0x530
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#define mmPCI_NRTR_LBW_RANGE_MASK_9 0x534
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#define mmPCI_NRTR_LBW_RANGE_MASK_10 0x538
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#define mmPCI_NRTR_LBW_RANGE_MASK_11 0x53C
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#define mmPCI_NRTR_LBW_RANGE_MASK_12 0x540
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#define mmPCI_NRTR_LBW_RANGE_MASK_13 0x544
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#define mmPCI_NRTR_LBW_RANGE_MASK_14 0x548
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#define mmPCI_NRTR_LBW_RANGE_MASK_15 0x54C
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#define mmPCI_NRTR_LBW_RANGE_BASE_0 0x550
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#define mmPCI_NRTR_LBW_RANGE_BASE_1 0x554
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#define mmPCI_NRTR_LBW_RANGE_BASE_2 0x558
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#define mmPCI_NRTR_LBW_RANGE_BASE_3 0x55C
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#define mmPCI_NRTR_LBW_RANGE_BASE_4 0x560
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#define mmPCI_NRTR_LBW_RANGE_BASE_5 0x564
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#define mmPCI_NRTR_LBW_RANGE_BASE_6 0x568
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#define mmPCI_NRTR_LBW_RANGE_BASE_7 0x56C
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#define mmPCI_NRTR_LBW_RANGE_BASE_8 0x570
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#define mmPCI_NRTR_LBW_RANGE_BASE_9 0x574
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#define mmPCI_NRTR_LBW_RANGE_BASE_10 0x578
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#define mmPCI_NRTR_LBW_RANGE_BASE_11 0x57C
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#define mmPCI_NRTR_LBW_RANGE_BASE_12 0x580
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#define mmPCI_NRTR_LBW_RANGE_BASE_13 0x584
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#define mmPCI_NRTR_LBW_RANGE_BASE_14 0x588
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#define mmPCI_NRTR_LBW_RANGE_BASE_15 0x58C
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#define mmPCI_NRTR_RGLTR 0x590
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#define mmPCI_NRTR_RGLTR_WR_RESULT 0x594
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#define mmPCI_NRTR_RGLTR_RD_RESULT 0x598
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#define mmPCI_NRTR_SCRAMB_EN 0x600
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#define mmPCI_NRTR_NON_LIN_SCRAMB 0x604
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#endif /* ASIC_REG_PCI_NRTR_REGS_H_ */
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