/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME_QM_REGS_H_
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#define ASIC_REG_MME_QM_REGS_H_
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/*
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*****************************************
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* MME_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmMME_QM_GLBL_CFG0 0xD8000
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#define mmMME_QM_GLBL_CFG1 0xD8004
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#define mmMME_QM_GLBL_PROT 0xD8008
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#define mmMME_QM_GLBL_ERR_CFG 0xD800C
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#define mmMME_QM_GLBL_ERR_ADDR_LO 0xD8010
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#define mmMME_QM_GLBL_ERR_ADDR_HI 0xD8014
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#define mmMME_QM_GLBL_ERR_WDATA 0xD8018
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#define mmMME_QM_GLBL_SECURE_PROPS 0xD801C
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#define mmMME_QM_GLBL_NON_SECURE_PROPS 0xD8020
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#define mmMME_QM_GLBL_STS0 0xD8024
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#define mmMME_QM_GLBL_STS1 0xD8028
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#define mmMME_QM_PQ_BASE_LO 0xD8060
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#define mmMME_QM_PQ_BASE_HI 0xD8064
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#define mmMME_QM_PQ_SIZE 0xD8068
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#define mmMME_QM_PQ_PI 0xD806C
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#define mmMME_QM_PQ_CI 0xD8070
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#define mmMME_QM_PQ_CFG0 0xD8074
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#define mmMME_QM_PQ_CFG1 0xD8078
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#define mmMME_QM_PQ_ARUSER 0xD807C
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#define mmMME_QM_PQ_PUSH0 0xD8080
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#define mmMME_QM_PQ_PUSH1 0xD8084
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#define mmMME_QM_PQ_PUSH2 0xD8088
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#define mmMME_QM_PQ_PUSH3 0xD808C
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#define mmMME_QM_PQ_STS0 0xD8090
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#define mmMME_QM_PQ_STS1 0xD8094
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#define mmMME_QM_PQ_RD_RATE_LIM_EN 0xD80A0
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#define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xD80A4
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#define mmMME_QM_PQ_RD_RATE_LIM_SAT 0xD80A8
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#define mmMME_QM_PQ_RD_RATE_LIM_TOUT 0xD80AC
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#define mmMME_QM_CQ_CFG0 0xD80B0
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#define mmMME_QM_CQ_CFG1 0xD80B4
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#define mmMME_QM_CQ_ARUSER 0xD80B8
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#define mmMME_QM_CQ_PTR_LO 0xD80C0
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#define mmMME_QM_CQ_PTR_HI 0xD80C4
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#define mmMME_QM_CQ_TSIZE 0xD80C8
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#define mmMME_QM_CQ_CTL 0xD80CC
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#define mmMME_QM_CQ_PTR_LO_STS 0xD80D4
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#define mmMME_QM_CQ_PTR_HI_STS 0xD80D8
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#define mmMME_QM_CQ_TSIZE_STS 0xD80DC
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#define mmMME_QM_CQ_CTL_STS 0xD80E0
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#define mmMME_QM_CQ_STS0 0xD80E4
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#define mmMME_QM_CQ_STS1 0xD80E8
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#define mmMME_QM_CQ_RD_RATE_LIM_EN 0xD80F0
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#define mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xD80F4
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#define mmMME_QM_CQ_RD_RATE_LIM_SAT 0xD80F8
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#define mmMME_QM_CQ_RD_RATE_LIM_TOUT 0xD80FC
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#define mmMME_QM_CQ_IFIFO_CNT 0xD8108
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#define mmMME_QM_CP_MSG_BASE0_ADDR_LO 0xD8120
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#define mmMME_QM_CP_MSG_BASE0_ADDR_HI 0xD8124
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#define mmMME_QM_CP_MSG_BASE1_ADDR_LO 0xD8128
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#define mmMME_QM_CP_MSG_BASE1_ADDR_HI 0xD812C
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#define mmMME_QM_CP_MSG_BASE2_ADDR_LO 0xD8130
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#define mmMME_QM_CP_MSG_BASE2_ADDR_HI 0xD8134
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#define mmMME_QM_CP_MSG_BASE3_ADDR_LO 0xD8138
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#define mmMME_QM_CP_MSG_BASE3_ADDR_HI 0xD813C
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#define mmMME_QM_CP_LDMA_TSIZE_OFFSET 0xD8140
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#define mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xD8144
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#define mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xD8148
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#define mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xD814C
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#define mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xD8150
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#define mmMME_QM_CP_LDMA_COMMIT_OFFSET 0xD8154
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#define mmMME_QM_CP_FENCE0_RDATA 0xD8158
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#define mmMME_QM_CP_FENCE1_RDATA 0xD815C
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#define mmMME_QM_CP_FENCE2_RDATA 0xD8160
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#define mmMME_QM_CP_FENCE3_RDATA 0xD8164
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#define mmMME_QM_CP_FENCE0_CNT 0xD8168
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#define mmMME_QM_CP_FENCE1_CNT 0xD816C
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#define mmMME_QM_CP_FENCE2_CNT 0xD8170
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#define mmMME_QM_CP_FENCE3_CNT 0xD8174
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#define mmMME_QM_CP_STS 0xD8178
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#define mmMME_QM_CP_CURRENT_INST_LO 0xD817C
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#define mmMME_QM_CP_CURRENT_INST_HI 0xD8180
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#define mmMME_QM_CP_BARRIER_CFG 0xD8184
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#define mmMME_QM_CP_DBG_0 0xD8188
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#define mmMME_QM_PQ_BUF_ADDR 0xD8300
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#define mmMME_QM_PQ_BUF_RDATA 0xD8304
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#define mmMME_QM_CQ_BUF_ADDR 0xD8308
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#define mmMME_QM_CQ_BUF_RDATA 0xD830C
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#endif /* ASIC_REG_MME_QM_REGS_H_ */
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