/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME4_RTR_REGS_H_
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#define ASIC_REG_MME4_RTR_REGS_H_
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/*
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*****************************************
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* MME4_RTR (Prototype: MME_RTR)
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*****************************************
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*/
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#define mmMME4_RTR_HBW_RD_RQ_E_ARB 0x100100
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#define mmMME4_RTR_HBW_RD_RQ_W_ARB 0x100104
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#define mmMME4_RTR_HBW_RD_RQ_N_ARB 0x100108
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#define mmMME4_RTR_HBW_RD_RQ_S_ARB 0x10010C
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#define mmMME4_RTR_HBW_RD_RQ_L_ARB 0x100110
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#define mmMME4_RTR_HBW_E_ARB_MAX 0x100120
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#define mmMME4_RTR_HBW_W_ARB_MAX 0x100124
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#define mmMME4_RTR_HBW_N_ARB_MAX 0x100128
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#define mmMME4_RTR_HBW_S_ARB_MAX 0x10012C
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#define mmMME4_RTR_HBW_L_ARB_MAX 0x100130
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#define mmMME4_RTR_HBW_RD_RS_MAX_CREDIT 0x100140
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#define mmMME4_RTR_HBW_WR_RQ_MAX_CREDIT 0x100144
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#define mmMME4_RTR_HBW_RD_RQ_MAX_CREDIT 0x100148
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#define mmMME4_RTR_HBW_RD_RS_E_ARB 0x100150
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#define mmMME4_RTR_HBW_RD_RS_W_ARB 0x100154
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#define mmMME4_RTR_HBW_RD_RS_N_ARB 0x100158
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#define mmMME4_RTR_HBW_RD_RS_S_ARB 0x10015C
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#define mmMME4_RTR_HBW_RD_RS_L_ARB 0x100160
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#define mmMME4_RTR_HBW_WR_RQ_E_ARB 0x100170
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#define mmMME4_RTR_HBW_WR_RQ_W_ARB 0x100174
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#define mmMME4_RTR_HBW_WR_RQ_N_ARB 0x100178
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#define mmMME4_RTR_HBW_WR_RQ_S_ARB 0x10017C
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#define mmMME4_RTR_HBW_WR_RQ_L_ARB 0x100180
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#define mmMME4_RTR_HBW_WR_RS_E_ARB 0x100190
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#define mmMME4_RTR_HBW_WR_RS_W_ARB 0x100194
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#define mmMME4_RTR_HBW_WR_RS_N_ARB 0x100198
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#define mmMME4_RTR_HBW_WR_RS_S_ARB 0x10019C
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#define mmMME4_RTR_HBW_WR_RS_L_ARB 0x1001A0
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#define mmMME4_RTR_LBW_RD_RQ_E_ARB 0x100200
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#define mmMME4_RTR_LBW_RD_RQ_W_ARB 0x100204
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#define mmMME4_RTR_LBW_RD_RQ_N_ARB 0x100208
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#define mmMME4_RTR_LBW_RD_RQ_S_ARB 0x10020C
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#define mmMME4_RTR_LBW_RD_RQ_L_ARB 0x100210
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#define mmMME4_RTR_LBW_E_ARB_MAX 0x100220
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#define mmMME4_RTR_LBW_W_ARB_MAX 0x100224
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#define mmMME4_RTR_LBW_N_ARB_MAX 0x100228
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#define mmMME4_RTR_LBW_S_ARB_MAX 0x10022C
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#define mmMME4_RTR_LBW_L_ARB_MAX 0x100230
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#define mmMME4_RTR_LBW_SRAM_MAX_CREDIT 0x100240
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#define mmMME4_RTR_LBW_RD_RS_E_ARB 0x100250
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#define mmMME4_RTR_LBW_RD_RS_W_ARB 0x100254
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#define mmMME4_RTR_LBW_RD_RS_N_ARB 0x100258
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#define mmMME4_RTR_LBW_RD_RS_S_ARB 0x10025C
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#define mmMME4_RTR_LBW_RD_RS_L_ARB 0x100260
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#define mmMME4_RTR_LBW_WR_RQ_E_ARB 0x100270
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#define mmMME4_RTR_LBW_WR_RQ_W_ARB 0x100274
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#define mmMME4_RTR_LBW_WR_RQ_N_ARB 0x100278
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#define mmMME4_RTR_LBW_WR_RQ_S_ARB 0x10027C
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#define mmMME4_RTR_LBW_WR_RQ_L_ARB 0x100280
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#define mmMME4_RTR_LBW_WR_RS_E_ARB 0x100290
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#define mmMME4_RTR_LBW_WR_RS_W_ARB 0x100294
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#define mmMME4_RTR_LBW_WR_RS_N_ARB 0x100298
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#define mmMME4_RTR_LBW_WR_RS_S_ARB 0x10029C
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#define mmMME4_RTR_LBW_WR_RS_L_ARB 0x1002A0
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#define mmMME4_RTR_DBG_E_ARB 0x100300
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#define mmMME4_RTR_DBG_W_ARB 0x100304
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#define mmMME4_RTR_DBG_N_ARB 0x100308
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#define mmMME4_RTR_DBG_S_ARB 0x10030C
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#define mmMME4_RTR_DBG_L_ARB 0x100310
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#define mmMME4_RTR_DBG_E_ARB_MAX 0x100320
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#define mmMME4_RTR_DBG_W_ARB_MAX 0x100324
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#define mmMME4_RTR_DBG_N_ARB_MAX 0x100328
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#define mmMME4_RTR_DBG_S_ARB_MAX 0x10032C
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#define mmMME4_RTR_DBG_L_ARB_MAX 0x100330
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#define mmMME4_RTR_SPLIT_COEF_0 0x100400
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#define mmMME4_RTR_SPLIT_COEF_1 0x100404
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#define mmMME4_RTR_SPLIT_COEF_2 0x100408
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#define mmMME4_RTR_SPLIT_COEF_3 0x10040C
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#define mmMME4_RTR_SPLIT_COEF_4 0x100410
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#define mmMME4_RTR_SPLIT_COEF_5 0x100414
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#define mmMME4_RTR_SPLIT_COEF_6 0x100418
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#define mmMME4_RTR_SPLIT_COEF_7 0x10041C
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#define mmMME4_RTR_SPLIT_COEF_8 0x100420
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#define mmMME4_RTR_SPLIT_COEF_9 0x100424
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#define mmMME4_RTR_SPLIT_CFG 0x100440
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#define mmMME4_RTR_SPLIT_RD_SAT 0x100444
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#define mmMME4_RTR_SPLIT_RD_RST_TOKEN 0x100448
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#define mmMME4_RTR_SPLIT_RD_TIMEOUT_0 0x10044C
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#define mmMME4_RTR_SPLIT_RD_TIMEOUT_1 0x100450
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#define mmMME4_RTR_SPLIT_WR_SAT 0x100454
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#define mmMME4_RTR_WPLIT_WR_TST_TOLEN 0x100458
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#define mmMME4_RTR_SPLIT_WR_TIMEOUT_0 0x10045C
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#define mmMME4_RTR_SPLIT_WR_TIMEOUT_1 0x100460
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#define mmMME4_RTR_HBW_RANGE_HIT 0x100470
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#define mmMME4_RTR_HBW_RANGE_MASK_L_0 0x100480
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#define mmMME4_RTR_HBW_RANGE_MASK_L_1 0x100484
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#define mmMME4_RTR_HBW_RANGE_MASK_L_2 0x100488
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#define mmMME4_RTR_HBW_RANGE_MASK_L_3 0x10048C
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#define mmMME4_RTR_HBW_RANGE_MASK_L_4 0x100490
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#define mmMME4_RTR_HBW_RANGE_MASK_L_5 0x100494
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#define mmMME4_RTR_HBW_RANGE_MASK_L_6 0x100498
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#define mmMME4_RTR_HBW_RANGE_MASK_L_7 0x10049C
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#define mmMME4_RTR_HBW_RANGE_MASK_H_0 0x1004A0
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#define mmMME4_RTR_HBW_RANGE_MASK_H_1 0x1004A4
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#define mmMME4_RTR_HBW_RANGE_MASK_H_2 0x1004A8
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#define mmMME4_RTR_HBW_RANGE_MASK_H_3 0x1004AC
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#define mmMME4_RTR_HBW_RANGE_MASK_H_4 0x1004B0
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#define mmMME4_RTR_HBW_RANGE_MASK_H_5 0x1004B4
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#define mmMME4_RTR_HBW_RANGE_MASK_H_6 0x1004B8
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#define mmMME4_RTR_HBW_RANGE_MASK_H_7 0x1004BC
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#define mmMME4_RTR_HBW_RANGE_BASE_L_0 0x1004C0
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#define mmMME4_RTR_HBW_RANGE_BASE_L_1 0x1004C4
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#define mmMME4_RTR_HBW_RANGE_BASE_L_2 0x1004C8
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#define mmMME4_RTR_HBW_RANGE_BASE_L_3 0x1004CC
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#define mmMME4_RTR_HBW_RANGE_BASE_L_4 0x1004D0
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#define mmMME4_RTR_HBW_RANGE_BASE_L_5 0x1004D4
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#define mmMME4_RTR_HBW_RANGE_BASE_L_6 0x1004D8
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#define mmMME4_RTR_HBW_RANGE_BASE_L_7 0x1004DC
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#define mmMME4_RTR_HBW_RANGE_BASE_H_0 0x1004E0
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#define mmMME4_RTR_HBW_RANGE_BASE_H_1 0x1004E4
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#define mmMME4_RTR_HBW_RANGE_BASE_H_2 0x1004E8
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#define mmMME4_RTR_HBW_RANGE_BASE_H_3 0x1004EC
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#define mmMME4_RTR_HBW_RANGE_BASE_H_4 0x1004F0
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#define mmMME4_RTR_HBW_RANGE_BASE_H_5 0x1004F4
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#define mmMME4_RTR_HBW_RANGE_BASE_H_6 0x1004F8
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#define mmMME4_RTR_HBW_RANGE_BASE_H_7 0x1004FC
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#define mmMME4_RTR_LBW_RANGE_HIT 0x100500
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#define mmMME4_RTR_LBW_RANGE_MASK_0 0x100510
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#define mmMME4_RTR_LBW_RANGE_MASK_1 0x100514
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#define mmMME4_RTR_LBW_RANGE_MASK_2 0x100518
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#define mmMME4_RTR_LBW_RANGE_MASK_3 0x10051C
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#define mmMME4_RTR_LBW_RANGE_MASK_4 0x100520
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#define mmMME4_RTR_LBW_RANGE_MASK_5 0x100524
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#define mmMME4_RTR_LBW_RANGE_MASK_6 0x100528
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#define mmMME4_RTR_LBW_RANGE_MASK_7 0x10052C
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#define mmMME4_RTR_LBW_RANGE_MASK_8 0x100530
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#define mmMME4_RTR_LBW_RANGE_MASK_9 0x100534
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#define mmMME4_RTR_LBW_RANGE_MASK_10 0x100538
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#define mmMME4_RTR_LBW_RANGE_MASK_11 0x10053C
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#define mmMME4_RTR_LBW_RANGE_MASK_12 0x100540
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#define mmMME4_RTR_LBW_RANGE_MASK_13 0x100544
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#define mmMME4_RTR_LBW_RANGE_MASK_14 0x100548
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#define mmMME4_RTR_LBW_RANGE_MASK_15 0x10054C
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#define mmMME4_RTR_LBW_RANGE_BASE_0 0x100550
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#define mmMME4_RTR_LBW_RANGE_BASE_1 0x100554
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#define mmMME4_RTR_LBW_RANGE_BASE_2 0x100558
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#define mmMME4_RTR_LBW_RANGE_BASE_3 0x10055C
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#define mmMME4_RTR_LBW_RANGE_BASE_4 0x100560
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#define mmMME4_RTR_LBW_RANGE_BASE_5 0x100564
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#define mmMME4_RTR_LBW_RANGE_BASE_6 0x100568
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#define mmMME4_RTR_LBW_RANGE_BASE_7 0x10056C
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#define mmMME4_RTR_LBW_RANGE_BASE_8 0x100570
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#define mmMME4_RTR_LBW_RANGE_BASE_9 0x100574
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#define mmMME4_RTR_LBW_RANGE_BASE_10 0x100578
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#define mmMME4_RTR_LBW_RANGE_BASE_11 0x10057C
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#define mmMME4_RTR_LBW_RANGE_BASE_12 0x100580
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#define mmMME4_RTR_LBW_RANGE_BASE_13 0x100584
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#define mmMME4_RTR_LBW_RANGE_BASE_14 0x100588
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#define mmMME4_RTR_LBW_RANGE_BASE_15 0x10058C
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#define mmMME4_RTR_RGLTR 0x100590
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#define mmMME4_RTR_RGLTR_WR_RESULT 0x100594
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#define mmMME4_RTR_RGLTR_RD_RESULT 0x100598
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#define mmMME4_RTR_SCRAMB_EN 0x100600
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#define mmMME4_RTR_NON_LIN_SCRAMB 0x100604
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#endif /* ASIC_REG_MME4_RTR_REGS_H_ */
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