/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME3_RTR_REGS_H_
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#define ASIC_REG_MME3_RTR_REGS_H_
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/*
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*****************************************
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* MME3_RTR (Prototype: MME_RTR)
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*****************************************
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*/
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#define mmMME3_RTR_HBW_RD_RQ_E_ARB 0xC0100
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#define mmMME3_RTR_HBW_RD_RQ_W_ARB 0xC0104
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#define mmMME3_RTR_HBW_RD_RQ_N_ARB 0xC0108
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#define mmMME3_RTR_HBW_RD_RQ_S_ARB 0xC010C
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#define mmMME3_RTR_HBW_RD_RQ_L_ARB 0xC0110
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#define mmMME3_RTR_HBW_E_ARB_MAX 0xC0120
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#define mmMME3_RTR_HBW_W_ARB_MAX 0xC0124
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#define mmMME3_RTR_HBW_N_ARB_MAX 0xC0128
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#define mmMME3_RTR_HBW_S_ARB_MAX 0xC012C
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#define mmMME3_RTR_HBW_L_ARB_MAX 0xC0130
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#define mmMME3_RTR_HBW_RD_RS_MAX_CREDIT 0xC0140
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#define mmMME3_RTR_HBW_WR_RQ_MAX_CREDIT 0xC0144
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#define mmMME3_RTR_HBW_RD_RQ_MAX_CREDIT 0xC0148
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#define mmMME3_RTR_HBW_RD_RS_E_ARB 0xC0150
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#define mmMME3_RTR_HBW_RD_RS_W_ARB 0xC0154
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#define mmMME3_RTR_HBW_RD_RS_N_ARB 0xC0158
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#define mmMME3_RTR_HBW_RD_RS_S_ARB 0xC015C
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#define mmMME3_RTR_HBW_RD_RS_L_ARB 0xC0160
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#define mmMME3_RTR_HBW_WR_RQ_E_ARB 0xC0170
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#define mmMME3_RTR_HBW_WR_RQ_W_ARB 0xC0174
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#define mmMME3_RTR_HBW_WR_RQ_N_ARB 0xC0178
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#define mmMME3_RTR_HBW_WR_RQ_S_ARB 0xC017C
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#define mmMME3_RTR_HBW_WR_RQ_L_ARB 0xC0180
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#define mmMME3_RTR_HBW_WR_RS_E_ARB 0xC0190
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#define mmMME3_RTR_HBW_WR_RS_W_ARB 0xC0194
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#define mmMME3_RTR_HBW_WR_RS_N_ARB 0xC0198
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#define mmMME3_RTR_HBW_WR_RS_S_ARB 0xC019C
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#define mmMME3_RTR_HBW_WR_RS_L_ARB 0xC01A0
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#define mmMME3_RTR_LBW_RD_RQ_E_ARB 0xC0200
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#define mmMME3_RTR_LBW_RD_RQ_W_ARB 0xC0204
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#define mmMME3_RTR_LBW_RD_RQ_N_ARB 0xC0208
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#define mmMME3_RTR_LBW_RD_RQ_S_ARB 0xC020C
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#define mmMME3_RTR_LBW_RD_RQ_L_ARB 0xC0210
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#define mmMME3_RTR_LBW_E_ARB_MAX 0xC0220
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#define mmMME3_RTR_LBW_W_ARB_MAX 0xC0224
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#define mmMME3_RTR_LBW_N_ARB_MAX 0xC0228
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#define mmMME3_RTR_LBW_S_ARB_MAX 0xC022C
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#define mmMME3_RTR_LBW_L_ARB_MAX 0xC0230
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#define mmMME3_RTR_LBW_SRAM_MAX_CREDIT 0xC0240
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#define mmMME3_RTR_LBW_RD_RS_E_ARB 0xC0250
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#define mmMME3_RTR_LBW_RD_RS_W_ARB 0xC0254
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#define mmMME3_RTR_LBW_RD_RS_N_ARB 0xC0258
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#define mmMME3_RTR_LBW_RD_RS_S_ARB 0xC025C
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#define mmMME3_RTR_LBW_RD_RS_L_ARB 0xC0260
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#define mmMME3_RTR_LBW_WR_RQ_E_ARB 0xC0270
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#define mmMME3_RTR_LBW_WR_RQ_W_ARB 0xC0274
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#define mmMME3_RTR_LBW_WR_RQ_N_ARB 0xC0278
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#define mmMME3_RTR_LBW_WR_RQ_S_ARB 0xC027C
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#define mmMME3_RTR_LBW_WR_RQ_L_ARB 0xC0280
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#define mmMME3_RTR_LBW_WR_RS_E_ARB 0xC0290
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#define mmMME3_RTR_LBW_WR_RS_W_ARB 0xC0294
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#define mmMME3_RTR_LBW_WR_RS_N_ARB 0xC0298
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#define mmMME3_RTR_LBW_WR_RS_S_ARB 0xC029C
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#define mmMME3_RTR_LBW_WR_RS_L_ARB 0xC02A0
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#define mmMME3_RTR_DBG_E_ARB 0xC0300
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#define mmMME3_RTR_DBG_W_ARB 0xC0304
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#define mmMME3_RTR_DBG_N_ARB 0xC0308
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#define mmMME3_RTR_DBG_S_ARB 0xC030C
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#define mmMME3_RTR_DBG_L_ARB 0xC0310
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#define mmMME3_RTR_DBG_E_ARB_MAX 0xC0320
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#define mmMME3_RTR_DBG_W_ARB_MAX 0xC0324
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#define mmMME3_RTR_DBG_N_ARB_MAX 0xC0328
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#define mmMME3_RTR_DBG_S_ARB_MAX 0xC032C
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#define mmMME3_RTR_DBG_L_ARB_MAX 0xC0330
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#define mmMME3_RTR_SPLIT_COEF_0 0xC0400
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#define mmMME3_RTR_SPLIT_COEF_1 0xC0404
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#define mmMME3_RTR_SPLIT_COEF_2 0xC0408
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#define mmMME3_RTR_SPLIT_COEF_3 0xC040C
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#define mmMME3_RTR_SPLIT_COEF_4 0xC0410
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#define mmMME3_RTR_SPLIT_COEF_5 0xC0414
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#define mmMME3_RTR_SPLIT_COEF_6 0xC0418
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#define mmMME3_RTR_SPLIT_COEF_7 0xC041C
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#define mmMME3_RTR_SPLIT_COEF_8 0xC0420
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#define mmMME3_RTR_SPLIT_COEF_9 0xC0424
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#define mmMME3_RTR_SPLIT_CFG 0xC0440
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#define mmMME3_RTR_SPLIT_RD_SAT 0xC0444
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#define mmMME3_RTR_SPLIT_RD_RST_TOKEN 0xC0448
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#define mmMME3_RTR_SPLIT_RD_TIMEOUT_0 0xC044C
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#define mmMME3_RTR_SPLIT_RD_TIMEOUT_1 0xC0450
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#define mmMME3_RTR_SPLIT_WR_SAT 0xC0454
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#define mmMME3_RTR_WPLIT_WR_TST_TOLEN 0xC0458
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#define mmMME3_RTR_SPLIT_WR_TIMEOUT_0 0xC045C
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#define mmMME3_RTR_SPLIT_WR_TIMEOUT_1 0xC0460
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#define mmMME3_RTR_HBW_RANGE_HIT 0xC0470
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#define mmMME3_RTR_HBW_RANGE_MASK_L_0 0xC0480
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#define mmMME3_RTR_HBW_RANGE_MASK_L_1 0xC0484
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#define mmMME3_RTR_HBW_RANGE_MASK_L_2 0xC0488
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#define mmMME3_RTR_HBW_RANGE_MASK_L_3 0xC048C
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#define mmMME3_RTR_HBW_RANGE_MASK_L_4 0xC0490
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#define mmMME3_RTR_HBW_RANGE_MASK_L_5 0xC0494
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#define mmMME3_RTR_HBW_RANGE_MASK_L_6 0xC0498
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#define mmMME3_RTR_HBW_RANGE_MASK_L_7 0xC049C
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#define mmMME3_RTR_HBW_RANGE_MASK_H_0 0xC04A0
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#define mmMME3_RTR_HBW_RANGE_MASK_H_1 0xC04A4
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#define mmMME3_RTR_HBW_RANGE_MASK_H_2 0xC04A8
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#define mmMME3_RTR_HBW_RANGE_MASK_H_3 0xC04AC
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#define mmMME3_RTR_HBW_RANGE_MASK_H_4 0xC04B0
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#define mmMME3_RTR_HBW_RANGE_MASK_H_5 0xC04B4
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#define mmMME3_RTR_HBW_RANGE_MASK_H_6 0xC04B8
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#define mmMME3_RTR_HBW_RANGE_MASK_H_7 0xC04BC
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#define mmMME3_RTR_HBW_RANGE_BASE_L_0 0xC04C0
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#define mmMME3_RTR_HBW_RANGE_BASE_L_1 0xC04C4
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#define mmMME3_RTR_HBW_RANGE_BASE_L_2 0xC04C8
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#define mmMME3_RTR_HBW_RANGE_BASE_L_3 0xC04CC
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#define mmMME3_RTR_HBW_RANGE_BASE_L_4 0xC04D0
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#define mmMME3_RTR_HBW_RANGE_BASE_L_5 0xC04D4
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#define mmMME3_RTR_HBW_RANGE_BASE_L_6 0xC04D8
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#define mmMME3_RTR_HBW_RANGE_BASE_L_7 0xC04DC
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#define mmMME3_RTR_HBW_RANGE_BASE_H_0 0xC04E0
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#define mmMME3_RTR_HBW_RANGE_BASE_H_1 0xC04E4
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#define mmMME3_RTR_HBW_RANGE_BASE_H_2 0xC04E8
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#define mmMME3_RTR_HBW_RANGE_BASE_H_3 0xC04EC
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#define mmMME3_RTR_HBW_RANGE_BASE_H_4 0xC04F0
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#define mmMME3_RTR_HBW_RANGE_BASE_H_5 0xC04F4
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#define mmMME3_RTR_HBW_RANGE_BASE_H_6 0xC04F8
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#define mmMME3_RTR_HBW_RANGE_BASE_H_7 0xC04FC
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#define mmMME3_RTR_LBW_RANGE_HIT 0xC0500
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#define mmMME3_RTR_LBW_RANGE_MASK_0 0xC0510
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#define mmMME3_RTR_LBW_RANGE_MASK_1 0xC0514
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#define mmMME3_RTR_LBW_RANGE_MASK_2 0xC0518
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#define mmMME3_RTR_LBW_RANGE_MASK_3 0xC051C
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#define mmMME3_RTR_LBW_RANGE_MASK_4 0xC0520
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#define mmMME3_RTR_LBW_RANGE_MASK_5 0xC0524
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#define mmMME3_RTR_LBW_RANGE_MASK_6 0xC0528
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#define mmMME3_RTR_LBW_RANGE_MASK_7 0xC052C
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#define mmMME3_RTR_LBW_RANGE_MASK_8 0xC0530
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#define mmMME3_RTR_LBW_RANGE_MASK_9 0xC0534
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#define mmMME3_RTR_LBW_RANGE_MASK_10 0xC0538
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#define mmMME3_RTR_LBW_RANGE_MASK_11 0xC053C
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#define mmMME3_RTR_LBW_RANGE_MASK_12 0xC0540
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#define mmMME3_RTR_LBW_RANGE_MASK_13 0xC0544
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#define mmMME3_RTR_LBW_RANGE_MASK_14 0xC0548
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#define mmMME3_RTR_LBW_RANGE_MASK_15 0xC054C
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#define mmMME3_RTR_LBW_RANGE_BASE_0 0xC0550
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#define mmMME3_RTR_LBW_RANGE_BASE_1 0xC0554
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#define mmMME3_RTR_LBW_RANGE_BASE_2 0xC0558
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#define mmMME3_RTR_LBW_RANGE_BASE_3 0xC055C
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#define mmMME3_RTR_LBW_RANGE_BASE_4 0xC0560
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#define mmMME3_RTR_LBW_RANGE_BASE_5 0xC0564
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#define mmMME3_RTR_LBW_RANGE_BASE_6 0xC0568
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#define mmMME3_RTR_LBW_RANGE_BASE_7 0xC056C
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#define mmMME3_RTR_LBW_RANGE_BASE_8 0xC0570
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#define mmMME3_RTR_LBW_RANGE_BASE_9 0xC0574
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#define mmMME3_RTR_LBW_RANGE_BASE_10 0xC0578
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#define mmMME3_RTR_LBW_RANGE_BASE_11 0xC057C
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#define mmMME3_RTR_LBW_RANGE_BASE_12 0xC0580
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#define mmMME3_RTR_LBW_RANGE_BASE_13 0xC0584
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#define mmMME3_RTR_LBW_RANGE_BASE_14 0xC0588
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#define mmMME3_RTR_LBW_RANGE_BASE_15 0xC058C
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#define mmMME3_RTR_RGLTR 0xC0590
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#define mmMME3_RTR_RGLTR_WR_RESULT 0xC0594
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#define mmMME3_RTR_RGLTR_RD_RESULT 0xC0598
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#define mmMME3_RTR_SCRAMB_EN 0xC0600
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#define mmMME3_RTR_NON_LIN_SCRAMB 0xC0604
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#endif /* ASIC_REG_MME3_RTR_REGS_H_ */
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