/* SPDX-License-Identifier: GPL-2.0
|
*
|
* Copyright 2016-2018 HabanaLabs, Ltd.
|
* All Rights Reserved.
|
*
|
*/
|
|
/************************************
|
** This is an auto-generated file **
|
** DO NOT EDIT BELOW **
|
************************************/
|
|
#ifndef ASIC_REG_MC_PLL_REGS_H_
|
#define ASIC_REG_MC_PLL_REGS_H_
|
|
/*
|
*****************************************
|
* MC_PLL (Prototype: PLL)
|
*****************************************
|
*/
|
|
#define mmMC_PLL_NR 0x4A1100
|
|
#define mmMC_PLL_NF 0x4A1104
|
|
#define mmMC_PLL_OD 0x4A1108
|
|
#define mmMC_PLL_NB 0x4A110C
|
|
#define mmMC_PLL_CFG 0x4A1110
|
|
#define mmMC_PLL_LOSE_MASK 0x4A1120
|
|
#define mmMC_PLL_LOCK_INTR 0x4A1128
|
|
#define mmMC_PLL_LOCK_BYPASS 0x4A112C
|
|
#define mmMC_PLL_DATA_CHNG 0x4A1130
|
|
#define mmMC_PLL_RST 0x4A1134
|
|
#define mmMC_PLL_SLIP_WD_CNTR 0x4A1150
|
|
#define mmMC_PLL_DIV_FACTOR_0 0x4A1200
|
|
#define mmMC_PLL_DIV_FACTOR_1 0x4A1204
|
|
#define mmMC_PLL_DIV_FACTOR_2 0x4A1208
|
|
#define mmMC_PLL_DIV_FACTOR_3 0x4A120C
|
|
#define mmMC_PLL_DIV_FACTOR_CMD_0 0x4A1220
|
|
#define mmMC_PLL_DIV_FACTOR_CMD_1 0x4A1224
|
|
#define mmMC_PLL_DIV_FACTOR_CMD_2 0x4A1228
|
|
#define mmMC_PLL_DIV_FACTOR_CMD_3 0x4A122C
|
|
#define mmMC_PLL_DIV_SEL_0 0x4A1280
|
|
#define mmMC_PLL_DIV_SEL_1 0x4A1284
|
|
#define mmMC_PLL_DIV_SEL_2 0x4A1288
|
|
#define mmMC_PLL_DIV_SEL_3 0x4A128C
|
|
#define mmMC_PLL_DIV_EN_0 0x4A12A0
|
|
#define mmMC_PLL_DIV_EN_1 0x4A12A4
|
|
#define mmMC_PLL_DIV_EN_2 0x4A12A8
|
|
#define mmMC_PLL_DIV_EN_3 0x4A12AC
|
|
#define mmMC_PLL_DIV_FACTOR_BUSY_0 0x4A12C0
|
|
#define mmMC_PLL_DIV_FACTOR_BUSY_1 0x4A12C4
|
|
#define mmMC_PLL_DIV_FACTOR_BUSY_2 0x4A12C8
|
|
#define mmMC_PLL_DIV_FACTOR_BUSY_3 0x4A12CC
|
|
#define mmMC_PLL_CLK_GATER 0x4A1300
|
|
#define mmMC_PLL_CLK_RLX_0 0x4A1310
|
|
#define mmMC_PLL_CLK_RLX_1 0x4A1314
|
|
#define mmMC_PLL_CLK_RLX_2 0x4A1318
|
|
#define mmMC_PLL_CLK_RLX_3 0x4A131C
|
|
#define mmMC_PLL_REF_CNTR_PERIOD 0x4A1400
|
|
#define mmMC_PLL_REF_LOW_THRESHOLD 0x4A1410
|
|
#define mmMC_PLL_REF_HIGH_THRESHOLD 0x4A1420
|
|
#define mmMC_PLL_PLL_NOT_STABLE 0x4A1430
|
|
#define mmMC_PLL_FREQ_CALC_EN 0x4A1440
|
|
#endif /* ASIC_REG_MC_PLL_REGS_H_ */
|
