/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_NRTR_REGS_H_
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#define ASIC_REG_DMA_NRTR_REGS_H_
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/*
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*****************************************
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* DMA_NRTR (Prototype: IF_NRTR)
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*****************************************
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*/
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#define mmDMA_NRTR_HBW_MAX_CRED 0x1C0100
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#define mmDMA_NRTR_LBW_MAX_CRED 0x1C0120
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#define mmDMA_NRTR_DBG_E_ARB 0x1C0300
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#define mmDMA_NRTR_DBG_W_ARB 0x1C0304
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#define mmDMA_NRTR_DBG_N_ARB 0x1C0308
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#define mmDMA_NRTR_DBG_S_ARB 0x1C030C
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#define mmDMA_NRTR_DBG_L_ARB 0x1C0310
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#define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C0320
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#define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C0324
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#define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C0328
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#define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C
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#define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C0330
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#define mmDMA_NRTR_SPLIT_COEF_0 0x1C0400
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#define mmDMA_NRTR_SPLIT_COEF_1 0x1C0404
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#define mmDMA_NRTR_SPLIT_COEF_2 0x1C0408
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#define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C
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#define mmDMA_NRTR_SPLIT_COEF_4 0x1C0410
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#define mmDMA_NRTR_SPLIT_COEF_5 0x1C0414
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#define mmDMA_NRTR_SPLIT_COEF_6 0x1C0418
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#define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C
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#define mmDMA_NRTR_SPLIT_COEF_8 0x1C0420
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#define mmDMA_NRTR_SPLIT_COEF_9 0x1C0424
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#define mmDMA_NRTR_SPLIT_CFG 0x1C0440
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#define mmDMA_NRTR_SPLIT_RD_SAT 0x1C0444
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#define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C0448
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#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C
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#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C0450
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#define mmDMA_NRTR_SPLIT_WR_SAT 0x1C0454
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#define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C0458
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#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C
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#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C0460
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#define mmDMA_NRTR_HBW_RANGE_HIT 0x1C0470
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C0480
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C0484
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C0488
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C0490
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C0494
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C0498
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#define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8
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#define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8
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#define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8
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#define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC
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#define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500
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#define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510
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#define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514
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#define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518
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#define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C
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#define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520
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#define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524
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#define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528
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#define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C
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#define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530
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#define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534
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#define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538
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#define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C
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#define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540
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#define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544
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#define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548
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#define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C
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#define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550
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#define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554
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#define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558
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#define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C
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#define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560
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#define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564
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#define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568
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#define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C
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#define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570
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#define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574
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#define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578
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#define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C
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#define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580
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#define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584
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#define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588
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#define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C
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#define mmDMA_NRTR_RGLTR 0x1C0590
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#define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594
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#define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598
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#define mmDMA_NRTR_SCRAMB_EN 0x1C0600
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#define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604
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#endif /* ASIC_REG_DMA_NRTR_REGS_H_ */
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