/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_MACRO_MASKS_H_
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#define ASIC_REG_DMA_MACRO_MASKS_H_
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/*
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*****************************************
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* DMA_MACRO (Prototype: DMA_MACRO)
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*****************************************
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*/
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/* DMA_MACRO_LBW_RANGE_HIT_BLOCK */
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#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0
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#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF
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/* DMA_MACRO_LBW_RANGE_MASK */
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#define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0
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#define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF
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/* DMA_MACRO_LBW_RANGE_BASE */
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#define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0
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#define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF
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/* DMA_MACRO_HBW_RANGE_HIT_BLOCK */
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#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0
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#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF
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/* DMA_MACRO_HBW_RANGE_MASK_49_32 */
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#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0
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#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF
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/* DMA_MACRO_HBW_RANGE_MASK_31_0 */
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#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 0
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#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF
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/* DMA_MACRO_HBW_RANGE_BASE_49_32 */
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#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 0
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#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF
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/* DMA_MACRO_HBW_RANGE_BASE_31_0 */
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#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 0
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#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF
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/* DMA_MACRO_WRITE_EN */
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#define DMA_MACRO_WRITE_EN_R_SHIFT 0
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#define DMA_MACRO_WRITE_EN_R_MASK 0x1
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/* DMA_MACRO_WRITE_CREDIT */
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#define DMA_MACRO_WRITE_CREDIT_R_SHIFT 0
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#define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF
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/* DMA_MACRO_READ_EN */
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#define DMA_MACRO_READ_EN_R_SHIFT 0
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#define DMA_MACRO_READ_EN_R_MASK 0x1
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/* DMA_MACRO_READ_CREDIT */
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#define DMA_MACRO_READ_CREDIT_R_SHIFT 0
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#define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF
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/* DMA_MACRO_SRAM_BUSY */
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/* DMA_MACRO_RAZWI_LBW_WT_VLD */
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#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 0
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#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x1
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/* DMA_MACRO_RAZWI_LBW_WT_ID */
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#define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 0
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#define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF
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/* DMA_MACRO_RAZWI_LBW_RD_VLD */
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#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 0
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#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x1
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/* DMA_MACRO_RAZWI_LBW_RD_ID */
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#define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 0
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#define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF
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/* DMA_MACRO_RAZWI_HBW_WT_VLD */
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#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 0
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#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x1
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/* DMA_MACRO_RAZWI_HBW_WT_ID */
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#define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 0
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#define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF
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/* DMA_MACRO_RAZWI_HBW_RD_VLD */
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#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 0
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#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x1
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/* DMA_MACRO_RAZWI_HBW_RD_ID */
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#define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0
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#define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF
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#endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */
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