/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_CH_0_REGS_H_
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#define ASIC_REG_DMA_CH_0_REGS_H_
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/*
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*****************************************
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* DMA_CH_0 (Prototype: DMA_CH)
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*****************************************
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*/
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#define mmDMA_CH_0_CFG0 0x401000
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#define mmDMA_CH_0_CFG1 0x401004
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#define mmDMA_CH_0_ERRMSG_ADDR_LO 0x401008
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#define mmDMA_CH_0_ERRMSG_ADDR_HI 0x40100C
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#define mmDMA_CH_0_ERRMSG_WDATA 0x401010
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#define mmDMA_CH_0_RD_COMP_ADDR_LO 0x401014
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#define mmDMA_CH_0_RD_COMP_ADDR_HI 0x401018
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#define mmDMA_CH_0_RD_COMP_WDATA 0x40101C
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#define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020
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#define mmDMA_CH_0_WR_COMP_ADDR_HI 0x401024
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#define mmDMA_CH_0_WR_COMP_WDATA 0x401028
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#define mmDMA_CH_0_LDMA_SRC_ADDR_LO 0x40102C
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#define mmDMA_CH_0_LDMA_SRC_ADDR_HI 0x401030
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#define mmDMA_CH_0_LDMA_DST_ADDR_LO 0x401034
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#define mmDMA_CH_0_LDMA_DST_ADDR_HI 0x401038
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#define mmDMA_CH_0_LDMA_TSIZE 0x40103C
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#define mmDMA_CH_0_COMIT_TRANSFER 0x401040
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#define mmDMA_CH_0_STS0 0x401044
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#define mmDMA_CH_0_STS1 0x401048
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#define mmDMA_CH_0_STS2 0x40104C
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#define mmDMA_CH_0_STS3 0x401050
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#define mmDMA_CH_0_STS4 0x401054
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#define mmDMA_CH_0_SRC_ADDR_LO_STS 0x401058
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#define mmDMA_CH_0_SRC_ADDR_HI_STS 0x40105C
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#define mmDMA_CH_0_SRC_TSIZE_STS 0x401060
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#define mmDMA_CH_0_DST_ADDR_LO_STS 0x401064
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#define mmDMA_CH_0_DST_ADDR_HI_STS 0x401068
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#define mmDMA_CH_0_DST_TSIZE_STS 0x40106C
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#define mmDMA_CH_0_RD_RATE_LIM_EN 0x401070
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#define mmDMA_CH_0_RD_RATE_LIM_RST_TOKEN 0x401074
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#define mmDMA_CH_0_RD_RATE_LIM_SAT 0x401078
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#define mmDMA_CH_0_RD_RATE_LIM_TOUT 0x40107C
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#define mmDMA_CH_0_WR_RATE_LIM_EN 0x401080
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#define mmDMA_CH_0_WR_RATE_LIM_RST_TOKEN 0x401084
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#define mmDMA_CH_0_WR_RATE_LIM_SAT 0x401088
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#define mmDMA_CH_0_WR_RATE_LIM_TOUT 0x40108C
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#define mmDMA_CH_0_CFG2 0x401090
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#define mmDMA_CH_0_TDMA_CTL 0x401100
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#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_LO 0x401104
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#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_HI 0x401108
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#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_0 0x40110C
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#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_0 0x401110
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#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 0x401114
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#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_0 0x401118
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#define mmDMA_CH_0_TDMA_SRC_STRIDE_0 0x40111C
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#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_1 0x401120
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#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_1 0x401124
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#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 0x401128
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#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_1 0x40112C
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#define mmDMA_CH_0_TDMA_SRC_STRIDE_1 0x401130
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#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_2 0x401134
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#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_2 0x401138
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#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 0x40113C
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#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_2 0x401140
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#define mmDMA_CH_0_TDMA_SRC_STRIDE_2 0x401144
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#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_3 0x401148
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#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_3 0x40114C
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#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 0x401150
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#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_3 0x401154
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#define mmDMA_CH_0_TDMA_SRC_STRIDE_3 0x401158
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#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_4 0x40115C
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#define mmDMA_CH_0_TDMA_SRC_ROI_SIZE_4 0x401160
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#define mmDMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 0x401164
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#define mmDMA_CH_0_TDMA_SRC_START_OFFSET_4 0x401168
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#define mmDMA_CH_0_TDMA_SRC_STRIDE_4 0x40116C
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#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_LO 0x401170
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#define mmDMA_CH_0_TDMA_DST_BASE_ADDR_HI 0x401174
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#define mmDMA_CH_0_TDMA_DST_ROI_BASE_0 0x401178
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#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_0 0x40117C
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#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 0x401180
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#define mmDMA_CH_0_TDMA_DST_START_OFFSET_0 0x401184
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#define mmDMA_CH_0_TDMA_DST_STRIDE_0 0x401188
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#define mmDMA_CH_0_TDMA_DST_ROI_BASE_1 0x40118C
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#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_1 0x401190
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#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 0x401194
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#define mmDMA_CH_0_TDMA_DST_START_OFFSET_1 0x401198
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#define mmDMA_CH_0_TDMA_DST_STRIDE_1 0x40119C
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#define mmDMA_CH_0_TDMA_DST_ROI_BASE_2 0x4011A0
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#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_2 0x4011A4
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#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 0x4011A8
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#define mmDMA_CH_0_TDMA_DST_START_OFFSET_2 0x4011AC
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#define mmDMA_CH_0_TDMA_DST_STRIDE_2 0x4011B0
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#define mmDMA_CH_0_TDMA_DST_ROI_BASE_3 0x4011B4
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#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_3 0x4011B8
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#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 0x4011BC
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#define mmDMA_CH_0_TDMA_DST_START_OFFSET_3 0x4011C0
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#define mmDMA_CH_0_TDMA_DST_STRIDE_3 0x4011C4
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#define mmDMA_CH_0_TDMA_DST_ROI_BASE_4 0x4011C8
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#define mmDMA_CH_0_TDMA_DST_ROI_SIZE_4 0x4011CC
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#define mmDMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 0x4011D0
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#define mmDMA_CH_0_TDMA_DST_START_OFFSET_4 0x4011D4
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#define mmDMA_CH_0_TDMA_DST_STRIDE_4 0x4011D8
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#define mmDMA_CH_0_MEM_INIT_BUSY 0x4011FC
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#endif /* ASIC_REG_DMA_CH_0_REGS_H_ */
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