/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_
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#define ASIC_REG_CPU_CA53_CFG_REGS_H_
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/*
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*****************************************
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* CPU_CA53_CFG (Prototype: CA53_CFG)
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*****************************************
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*/
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#define mmCPU_CA53_CFG_ARM_CFG 0x441100
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#define mmCPU_CA53_CFG_RST_ADDR_LSB_0 0x441104
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#define mmCPU_CA53_CFG_RST_ADDR_LSB_1 0x441108
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#define mmCPU_CA53_CFG_RST_ADDR_MSB_0 0x441114
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#define mmCPU_CA53_CFG_RST_ADDR_MSB_1 0x441118
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#define mmCPU_CA53_CFG_ARM_RST_CONTROL 0x441124
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#define mmCPU_CA53_CFG_ARM_AFFINITY 0x441128
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#define mmCPU_CA53_CFG_ARM_DISABLE 0x44112C
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#define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE 0x441130
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#define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG 0x441134
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#define mmCPU_CA53_CFG_ARM_PWR_MNG 0x441138
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#define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR 0x44113C
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#define mmCPU_CA53_CFG_ARM_DBG_MODES 0x441140
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#define mmCPU_CA53_CFG_ARM_PWR_STAT_0 0x441200
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#define mmCPU_CA53_CFG_ARM_PWR_STAT_1 0x441204
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#define mmCPU_CA53_CFG_ARM_DBG_STATUS 0x441208
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#define mmCPU_CA53_CFG_ARM_MEM_ATTR 0x44120C
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#define mmCPU_CA53_CFG_ARM_PMU_0 0x441210
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#define mmCPU_CA53_CFG_ARM_PMU_1 0x441214
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#endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */
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