/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC7_QM_REGS_H_
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#define ASIC_REG_TPC7_QM_REGS_H_
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/*
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*****************************************
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* TPC7_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC7_QM_GLBL_CFG0 0xFC8000
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#define mmTPC7_QM_GLBL_CFG1 0xFC8004
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#define mmTPC7_QM_GLBL_PROT 0xFC8008
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#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C
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#define mmTPC7_QM_GLBL_SECURE_PROPS_0 0xFC8010
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#define mmTPC7_QM_GLBL_SECURE_PROPS_1 0xFC8014
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#define mmTPC7_QM_GLBL_SECURE_PROPS_2 0xFC8018
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#define mmTPC7_QM_GLBL_SECURE_PROPS_3 0xFC801C
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#define mmTPC7_QM_GLBL_SECURE_PROPS_4 0xFC8020
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 0xFC8024
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 0xFC8028
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 0xFC802C
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 0xFC8030
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#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 0xFC8034
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#define mmTPC7_QM_GLBL_STS0 0xFC8038
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#define mmTPC7_QM_GLBL_STS1_0 0xFC8040
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#define mmTPC7_QM_GLBL_STS1_1 0xFC8044
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#define mmTPC7_QM_GLBL_STS1_2 0xFC8048
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#define mmTPC7_QM_GLBL_STS1_3 0xFC804C
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#define mmTPC7_QM_GLBL_STS1_4 0xFC8050
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#define mmTPC7_QM_GLBL_MSG_EN_0 0xFC8054
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#define mmTPC7_QM_GLBL_MSG_EN_1 0xFC8058
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#define mmTPC7_QM_GLBL_MSG_EN_2 0xFC805C
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#define mmTPC7_QM_GLBL_MSG_EN_3 0xFC8060
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#define mmTPC7_QM_GLBL_MSG_EN_4 0xFC8068
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#define mmTPC7_QM_PQ_BASE_LO_0 0xFC8070
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#define mmTPC7_QM_PQ_BASE_LO_1 0xFC8074
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#define mmTPC7_QM_PQ_BASE_LO_2 0xFC8078
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#define mmTPC7_QM_PQ_BASE_LO_3 0xFC807C
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#define mmTPC7_QM_PQ_BASE_HI_0 0xFC8080
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#define mmTPC7_QM_PQ_BASE_HI_1 0xFC8084
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#define mmTPC7_QM_PQ_BASE_HI_2 0xFC8088
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#define mmTPC7_QM_PQ_BASE_HI_3 0xFC808C
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#define mmTPC7_QM_PQ_SIZE_0 0xFC8090
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#define mmTPC7_QM_PQ_SIZE_1 0xFC8094
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#define mmTPC7_QM_PQ_SIZE_2 0xFC8098
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#define mmTPC7_QM_PQ_SIZE_3 0xFC809C
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#define mmTPC7_QM_PQ_PI_0 0xFC80A0
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#define mmTPC7_QM_PQ_PI_1 0xFC80A4
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#define mmTPC7_QM_PQ_PI_2 0xFC80A8
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#define mmTPC7_QM_PQ_PI_3 0xFC80AC
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#define mmTPC7_QM_PQ_CI_0 0xFC80B0
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#define mmTPC7_QM_PQ_CI_1 0xFC80B4
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#define mmTPC7_QM_PQ_CI_2 0xFC80B8
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#define mmTPC7_QM_PQ_CI_3 0xFC80BC
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#define mmTPC7_QM_PQ_CFG0_0 0xFC80C0
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#define mmTPC7_QM_PQ_CFG0_1 0xFC80C4
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#define mmTPC7_QM_PQ_CFG0_2 0xFC80C8
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#define mmTPC7_QM_PQ_CFG0_3 0xFC80CC
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#define mmTPC7_QM_PQ_CFG1_0 0xFC80D0
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#define mmTPC7_QM_PQ_CFG1_1 0xFC80D4
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#define mmTPC7_QM_PQ_CFG1_2 0xFC80D8
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#define mmTPC7_QM_PQ_CFG1_3 0xFC80DC
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#define mmTPC7_QM_PQ_ARUSER_31_11_0 0xFC80E0
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#define mmTPC7_QM_PQ_ARUSER_31_11_1 0xFC80E4
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#define mmTPC7_QM_PQ_ARUSER_31_11_2 0xFC80E8
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#define mmTPC7_QM_PQ_ARUSER_31_11_3 0xFC80EC
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#define mmTPC7_QM_PQ_STS0_0 0xFC80F0
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#define mmTPC7_QM_PQ_STS0_1 0xFC80F4
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#define mmTPC7_QM_PQ_STS0_2 0xFC80F8
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#define mmTPC7_QM_PQ_STS0_3 0xFC80FC
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#define mmTPC7_QM_PQ_STS1_0 0xFC8100
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#define mmTPC7_QM_PQ_STS1_1 0xFC8104
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#define mmTPC7_QM_PQ_STS1_2 0xFC8108
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#define mmTPC7_QM_PQ_STS1_3 0xFC810C
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#define mmTPC7_QM_CQ_CFG0_0 0xFC8110
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#define mmTPC7_QM_CQ_CFG0_1 0xFC8114
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#define mmTPC7_QM_CQ_CFG0_2 0xFC8118
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#define mmTPC7_QM_CQ_CFG0_3 0xFC811C
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#define mmTPC7_QM_CQ_CFG0_4 0xFC8120
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#define mmTPC7_QM_CQ_CFG1_0 0xFC8124
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#define mmTPC7_QM_CQ_CFG1_1 0xFC8128
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#define mmTPC7_QM_CQ_CFG1_2 0xFC812C
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#define mmTPC7_QM_CQ_CFG1_3 0xFC8130
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#define mmTPC7_QM_CQ_CFG1_4 0xFC8134
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#define mmTPC7_QM_CQ_ARUSER_31_11_0 0xFC8138
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#define mmTPC7_QM_CQ_ARUSER_31_11_1 0xFC813C
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#define mmTPC7_QM_CQ_ARUSER_31_11_2 0xFC8140
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#define mmTPC7_QM_CQ_ARUSER_31_11_3 0xFC8144
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#define mmTPC7_QM_CQ_ARUSER_31_11_4 0xFC8148
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#define mmTPC7_QM_CQ_STS0_0 0xFC814C
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#define mmTPC7_QM_CQ_STS0_1 0xFC8150
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#define mmTPC7_QM_CQ_STS0_2 0xFC8154
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#define mmTPC7_QM_CQ_STS0_3 0xFC8158
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#define mmTPC7_QM_CQ_STS0_4 0xFC815C
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#define mmTPC7_QM_CQ_STS1_0 0xFC8160
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#define mmTPC7_QM_CQ_STS1_1 0xFC8164
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#define mmTPC7_QM_CQ_STS1_2 0xFC8168
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#define mmTPC7_QM_CQ_STS1_3 0xFC816C
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#define mmTPC7_QM_CQ_STS1_4 0xFC8170
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#define mmTPC7_QM_CQ_PTR_LO_0 0xFC8174
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#define mmTPC7_QM_CQ_PTR_HI_0 0xFC8178
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#define mmTPC7_QM_CQ_TSIZE_0 0xFC817C
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#define mmTPC7_QM_CQ_CTL_0 0xFC8180
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#define mmTPC7_QM_CQ_PTR_LO_1 0xFC8184
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#define mmTPC7_QM_CQ_PTR_HI_1 0xFC8188
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#define mmTPC7_QM_CQ_TSIZE_1 0xFC818C
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#define mmTPC7_QM_CQ_CTL_1 0xFC8190
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#define mmTPC7_QM_CQ_PTR_LO_2 0xFC8194
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#define mmTPC7_QM_CQ_PTR_HI_2 0xFC8198
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#define mmTPC7_QM_CQ_TSIZE_2 0xFC819C
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#define mmTPC7_QM_CQ_CTL_2 0xFC81A0
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#define mmTPC7_QM_CQ_PTR_LO_3 0xFC81A4
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#define mmTPC7_QM_CQ_PTR_HI_3 0xFC81A8
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#define mmTPC7_QM_CQ_TSIZE_3 0xFC81AC
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#define mmTPC7_QM_CQ_CTL_3 0xFC81B0
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#define mmTPC7_QM_CQ_PTR_LO_4 0xFC81B4
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#define mmTPC7_QM_CQ_PTR_HI_4 0xFC81B8
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#define mmTPC7_QM_CQ_TSIZE_4 0xFC81BC
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#define mmTPC7_QM_CQ_CTL_4 0xFC81C0
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#define mmTPC7_QM_CQ_PTR_LO_STS_0 0xFC81C4
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#define mmTPC7_QM_CQ_PTR_LO_STS_1 0xFC81C8
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#define mmTPC7_QM_CQ_PTR_LO_STS_2 0xFC81CC
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#define mmTPC7_QM_CQ_PTR_LO_STS_3 0xFC81D0
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#define mmTPC7_QM_CQ_PTR_LO_STS_4 0xFC81D4
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#define mmTPC7_QM_CQ_PTR_HI_STS_0 0xFC81D8
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#define mmTPC7_QM_CQ_PTR_HI_STS_1 0xFC81DC
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#define mmTPC7_QM_CQ_PTR_HI_STS_2 0xFC81E0
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#define mmTPC7_QM_CQ_PTR_HI_STS_3 0xFC81E4
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#define mmTPC7_QM_CQ_PTR_HI_STS_4 0xFC81E8
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#define mmTPC7_QM_CQ_TSIZE_STS_0 0xFC81EC
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#define mmTPC7_QM_CQ_TSIZE_STS_1 0xFC81F0
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#define mmTPC7_QM_CQ_TSIZE_STS_2 0xFC81F4
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#define mmTPC7_QM_CQ_TSIZE_STS_3 0xFC81F8
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#define mmTPC7_QM_CQ_TSIZE_STS_4 0xFC81FC
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#define mmTPC7_QM_CQ_CTL_STS_0 0xFC8200
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#define mmTPC7_QM_CQ_CTL_STS_1 0xFC8204
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#define mmTPC7_QM_CQ_CTL_STS_2 0xFC8208
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#define mmTPC7_QM_CQ_CTL_STS_3 0xFC820C
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#define mmTPC7_QM_CQ_CTL_STS_4 0xFC8210
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#define mmTPC7_QM_CQ_IFIFO_CNT_0 0xFC8214
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#define mmTPC7_QM_CQ_IFIFO_CNT_1 0xFC8218
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#define mmTPC7_QM_CQ_IFIFO_CNT_2 0xFC821C
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#define mmTPC7_QM_CQ_IFIFO_CNT_3 0xFC8220
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#define mmTPC7_QM_CQ_IFIFO_CNT_4 0xFC8224
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 0xFC8228
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 0xFC822C
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 0xFC8230
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 0xFC8234
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 0xFC8238
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 0xFC823C
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 0xFC8240
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 0xFC8244
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 0xFC8248
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#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 0xFC824C
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 0xFC8250
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 0xFC8254
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 0xFC8258
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 0xFC825C
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 0xFC8260
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 0xFC8264
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 0xFC8268
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 0xFC826C
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 0xFC8270
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#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 0xFC8274
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 0xFC8278
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 0xFC827C
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 0xFC8280
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 0xFC8284
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 0xFC8288
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 0xFC828C
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 0xFC8290
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 0xFC8294
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 0xFC8298
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#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 0xFC829C
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 0xFC82A0
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 0xFC82A4
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 0xFC82A8
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 0xFC82AC
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 0xFC82B0
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 0xFC82B4
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 0xFC82B8
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 0xFC82BC
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 0xFC82C0
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#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 0xFC82C4
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 0xFC82C8
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 0xFC82CC
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 0xFC82D0
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 0xFC82D4
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#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 0xFC82D8
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xFC82E0
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xFC82E4
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xFC82E8
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xFC82EC
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#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xFC82F0
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xFC82F4
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xFC82F8
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xFC82FC
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xFC8300
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#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xFC8304
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#define mmTPC7_QM_CP_FENCE0_RDATA_0 0xFC8308
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#define mmTPC7_QM_CP_FENCE0_RDATA_1 0xFC830C
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#define mmTPC7_QM_CP_FENCE0_RDATA_2 0xFC8310
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#define mmTPC7_QM_CP_FENCE0_RDATA_3 0xFC8314
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#define mmTPC7_QM_CP_FENCE0_RDATA_4 0xFC8318
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#define mmTPC7_QM_CP_FENCE1_RDATA_0 0xFC831C
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#define mmTPC7_QM_CP_FENCE1_RDATA_1 0xFC8320
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#define mmTPC7_QM_CP_FENCE1_RDATA_2 0xFC8324
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#define mmTPC7_QM_CP_FENCE1_RDATA_3 0xFC8328
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#define mmTPC7_QM_CP_FENCE1_RDATA_4 0xFC832C
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#define mmTPC7_QM_CP_FENCE2_RDATA_0 0xFC8330
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#define mmTPC7_QM_CP_FENCE2_RDATA_1 0xFC8334
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#define mmTPC7_QM_CP_FENCE2_RDATA_2 0xFC8338
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#define mmTPC7_QM_CP_FENCE2_RDATA_3 0xFC833C
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#define mmTPC7_QM_CP_FENCE2_RDATA_4 0xFC8340
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#define mmTPC7_QM_CP_FENCE3_RDATA_0 0xFC8344
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#define mmTPC7_QM_CP_FENCE3_RDATA_1 0xFC8348
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#define mmTPC7_QM_CP_FENCE3_RDATA_2 0xFC834C
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#define mmTPC7_QM_CP_FENCE3_RDATA_3 0xFC8350
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#define mmTPC7_QM_CP_FENCE3_RDATA_4 0xFC8354
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#define mmTPC7_QM_CP_FENCE0_CNT_0 0xFC8358
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#define mmTPC7_QM_CP_FENCE0_CNT_1 0xFC835C
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#define mmTPC7_QM_CP_FENCE0_CNT_2 0xFC8360
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#define mmTPC7_QM_CP_FENCE0_CNT_3 0xFC8364
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#define mmTPC7_QM_CP_FENCE0_CNT_4 0xFC8368
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#define mmTPC7_QM_CP_FENCE1_CNT_0 0xFC836C
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#define mmTPC7_QM_CP_FENCE1_CNT_1 0xFC8370
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#define mmTPC7_QM_CP_FENCE1_CNT_2 0xFC8374
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#define mmTPC7_QM_CP_FENCE1_CNT_3 0xFC8378
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#define mmTPC7_QM_CP_FENCE1_CNT_4 0xFC837C
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#define mmTPC7_QM_CP_FENCE2_CNT_0 0xFC8380
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#define mmTPC7_QM_CP_FENCE2_CNT_1 0xFC8384
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#define mmTPC7_QM_CP_FENCE2_CNT_2 0xFC8388
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#define mmTPC7_QM_CP_FENCE2_CNT_3 0xFC838C
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#define mmTPC7_QM_CP_FENCE2_CNT_4 0xFC8390
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#define mmTPC7_QM_CP_FENCE3_CNT_0 0xFC8394
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#define mmTPC7_QM_CP_FENCE3_CNT_1 0xFC8398
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#define mmTPC7_QM_CP_FENCE3_CNT_2 0xFC839C
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#define mmTPC7_QM_CP_FENCE3_CNT_3 0xFC83A0
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#define mmTPC7_QM_CP_FENCE3_CNT_4 0xFC83A4
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#define mmTPC7_QM_CP_STS_0 0xFC83A8
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#define mmTPC7_QM_CP_STS_1 0xFC83AC
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#define mmTPC7_QM_CP_STS_2 0xFC83B0
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#define mmTPC7_QM_CP_STS_3 0xFC83B4
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#define mmTPC7_QM_CP_STS_4 0xFC83B8
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#define mmTPC7_QM_CP_CURRENT_INST_LO_0 0xFC83BC
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#define mmTPC7_QM_CP_CURRENT_INST_LO_1 0xFC83C0
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#define mmTPC7_QM_CP_CURRENT_INST_LO_2 0xFC83C4
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#define mmTPC7_QM_CP_CURRENT_INST_LO_3 0xFC83C8
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#define mmTPC7_QM_CP_CURRENT_INST_LO_4 0xFC83CC
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#define mmTPC7_QM_CP_CURRENT_INST_HI_0 0xFC83D0
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#define mmTPC7_QM_CP_CURRENT_INST_HI_1 0xFC83D4
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#define mmTPC7_QM_CP_CURRENT_INST_HI_2 0xFC83D8
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#define mmTPC7_QM_CP_CURRENT_INST_HI_3 0xFC83DC
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#define mmTPC7_QM_CP_CURRENT_INST_HI_4 0xFC83E0
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#define mmTPC7_QM_CP_BARRIER_CFG_0 0xFC83F4
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#define mmTPC7_QM_CP_BARRIER_CFG_1 0xFC83F8
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#define mmTPC7_QM_CP_BARRIER_CFG_2 0xFC83FC
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#define mmTPC7_QM_CP_BARRIER_CFG_3 0xFC8400
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#define mmTPC7_QM_CP_BARRIER_CFG_4 0xFC8404
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#define mmTPC7_QM_CP_DBG_0_0 0xFC8408
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#define mmTPC7_QM_CP_DBG_0_1 0xFC840C
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#define mmTPC7_QM_CP_DBG_0_2 0xFC8410
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#define mmTPC7_QM_CP_DBG_0_3 0xFC8414
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#define mmTPC7_QM_CP_DBG_0_4 0xFC8418
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#define mmTPC7_QM_CP_ARUSER_31_11_0 0xFC841C
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#define mmTPC7_QM_CP_ARUSER_31_11_1 0xFC8420
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#define mmTPC7_QM_CP_ARUSER_31_11_2 0xFC8424
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#define mmTPC7_QM_CP_ARUSER_31_11_3 0xFC8428
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#define mmTPC7_QM_CP_ARUSER_31_11_4 0xFC842C
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#define mmTPC7_QM_CP_AWUSER_31_11_0 0xFC8430
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#define mmTPC7_QM_CP_AWUSER_31_11_1 0xFC8434
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#define mmTPC7_QM_CP_AWUSER_31_11_2 0xFC8438
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#define mmTPC7_QM_CP_AWUSER_31_11_3 0xFC843C
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#define mmTPC7_QM_CP_AWUSER_31_11_4 0xFC8440
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#define mmTPC7_QM_ARB_CFG_0 0xFC8A00
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#define mmTPC7_QM_ARB_CHOISE_Q_PUSH 0xFC8A04
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#define mmTPC7_QM_ARB_WRR_WEIGHT_0 0xFC8A08
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#define mmTPC7_QM_ARB_WRR_WEIGHT_1 0xFC8A0C
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#define mmTPC7_QM_ARB_WRR_WEIGHT_2 0xFC8A10
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#define mmTPC7_QM_ARB_WRR_WEIGHT_3 0xFC8A14
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#define mmTPC7_QM_ARB_CFG_1 0xFC8A18
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0 0xFC8A20
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1 0xFC8A24
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2 0xFC8A28
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3 0xFC8A2C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4 0xFC8A30
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5 0xFC8A34
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6 0xFC8A38
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7 0xFC8A3C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8 0xFC8A40
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9 0xFC8A44
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10 0xFC8A48
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11 0xFC8A4C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12 0xFC8A50
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13 0xFC8A54
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14 0xFC8A58
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15 0xFC8A5C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16 0xFC8A60
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17 0xFC8A64
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18 0xFC8A68
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19 0xFC8A6C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20 0xFC8A70
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21 0xFC8A74
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22 0xFC8A78
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23 0xFC8A7C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24 0xFC8A80
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25 0xFC8A84
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26 0xFC8A88
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27 0xFC8A8C
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28 0xFC8A90
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29 0xFC8A94
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30 0xFC8A98
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#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31 0xFC8A9C
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#define mmTPC7_QM_ARB_MST_CRED_INC 0xFC8AA0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xFC8AA4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xFC8AA8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xFC8AAC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xFC8AB0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xFC8AB4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xFC8AB8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xFC8ABC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xFC8AC0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xFC8AC4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xFC8AC8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xFC8ACC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xFC8AD0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xFC8AD4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xFC8AD8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xFC8ADC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xFC8AE0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xFC8AE4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xFC8AE8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xFC8AEC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xFC8AF0
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xFC8AF4
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xFC8AF8
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xFC8AFC
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xFC8B00
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xFC8B04
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xFC8B08
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xFC8B0C
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xFC8B10
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xFC8B14
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xFC8B18
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xFC8B1C
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#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xFC8B20
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#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xFC8B28
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#define mmTPC7_QM_ARB_MST_SLAVE_EN 0xFC8B2C
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#define mmTPC7_QM_ARB_MST_QUIET_PER 0xFC8B34
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#define mmTPC7_QM_ARB_SLV_CHOISE_WDT 0xFC8B38
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#define mmTPC7_QM_ARB_SLV_ID 0xFC8B3C
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#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT 0xFC8B44
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#define mmTPC7_QM_ARB_MSG_AWUSER_31_11 0xFC8B48
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#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP 0xFC8B4C
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#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xFC8B50
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#define mmTPC7_QM_ARB_BASE_LO 0xFC8B54
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#define mmTPC7_QM_ARB_BASE_HI 0xFC8B58
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#define mmTPC7_QM_ARB_STATE_STS 0xFC8B80
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#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS 0xFC8B84
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#define mmTPC7_QM_ARB_MSG_STS 0xFC8B88
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#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD 0xFC8B8C
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#define mmTPC7_QM_ARB_ERR_CAUSE 0xFC8B9C
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#define mmTPC7_QM_ARB_ERR_MSG_EN 0xFC8BA0
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#define mmTPC7_QM_ARB_ERR_STS_DRP 0xFC8BA8
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#define mmTPC7_QM_ARB_MST_CRED_STS_0 0xFC8BB0
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#define mmTPC7_QM_ARB_MST_CRED_STS_1 0xFC8BB4
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#define mmTPC7_QM_ARB_MST_CRED_STS_2 0xFC8BB8
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#define mmTPC7_QM_ARB_MST_CRED_STS_3 0xFC8BBC
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#define mmTPC7_QM_ARB_MST_CRED_STS_4 0xFC8BC0
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#define mmTPC7_QM_ARB_MST_CRED_STS_5 0xFC8BC4
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#define mmTPC7_QM_ARB_MST_CRED_STS_6 0xFC8BC8
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#define mmTPC7_QM_ARB_MST_CRED_STS_7 0xFC8BCC
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#define mmTPC7_QM_ARB_MST_CRED_STS_8 0xFC8BD0
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#define mmTPC7_QM_ARB_MST_CRED_STS_9 0xFC8BD4
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#define mmTPC7_QM_ARB_MST_CRED_STS_10 0xFC8BD8
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#define mmTPC7_QM_ARB_MST_CRED_STS_11 0xFC8BDC
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#define mmTPC7_QM_ARB_MST_CRED_STS_12 0xFC8BE0
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#define mmTPC7_QM_ARB_MST_CRED_STS_13 0xFC8BE4
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#define mmTPC7_QM_ARB_MST_CRED_STS_14 0xFC8BE8
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#define mmTPC7_QM_ARB_MST_CRED_STS_15 0xFC8BEC
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#define mmTPC7_QM_ARB_MST_CRED_STS_16 0xFC8BF0
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#define mmTPC7_QM_ARB_MST_CRED_STS_17 0xFC8BF4
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#define mmTPC7_QM_ARB_MST_CRED_STS_18 0xFC8BF8
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#define mmTPC7_QM_ARB_MST_CRED_STS_19 0xFC8BFC
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#define mmTPC7_QM_ARB_MST_CRED_STS_20 0xFC8C00
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#define mmTPC7_QM_ARB_MST_CRED_STS_21 0xFC8C04
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#define mmTPC7_QM_ARB_MST_CRED_STS_22 0xFC8C08
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#define mmTPC7_QM_ARB_MST_CRED_STS_23 0xFC8C0C
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#define mmTPC7_QM_ARB_MST_CRED_STS_24 0xFC8C10
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#define mmTPC7_QM_ARB_MST_CRED_STS_25 0xFC8C14
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#define mmTPC7_QM_ARB_MST_CRED_STS_26 0xFC8C18
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#define mmTPC7_QM_ARB_MST_CRED_STS_27 0xFC8C1C
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#define mmTPC7_QM_ARB_MST_CRED_STS_28 0xFC8C20
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#define mmTPC7_QM_ARB_MST_CRED_STS_29 0xFC8C24
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#define mmTPC7_QM_ARB_MST_CRED_STS_30 0xFC8C28
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#define mmTPC7_QM_ARB_MST_CRED_STS_31 0xFC8C2C
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#define mmTPC7_QM_CGM_CFG 0xFC8C70
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#define mmTPC7_QM_CGM_STS 0xFC8C74
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#define mmTPC7_QM_CGM_CFG1 0xFC8C78
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#define mmTPC7_QM_LOCAL_RANGE_BASE 0xFC8C80
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#define mmTPC7_QM_LOCAL_RANGE_SIZE 0xFC8C84
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#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG 0xFC8C90
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#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 0xFC8C94
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#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 0xFC8C98
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#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 0xFC8C9C
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#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 0xFC8CA0
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#define mmTPC7_QM_GLBL_AXCACHE 0xFC8CA4
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#define mmTPC7_QM_IND_GW_APB_CFG 0xFC8CB0
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#define mmTPC7_QM_IND_GW_APB_WDATA 0xFC8CB4
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#define mmTPC7_QM_IND_GW_APB_RDATA 0xFC8CB8
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#define mmTPC7_QM_IND_GW_APB_STATUS 0xFC8CBC
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#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8CD0
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#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8CD4
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#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8CD8
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#define mmTPC7_QM_GLBL_MEM_INIT_BUSY 0xFC8D00
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#endif /* ASIC_REG_TPC7_QM_REGS_H_ */
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