/* SPDX-License-Identifier: GPL-2.0
|
*
|
* Copyright 2016-2018 HabanaLabs, Ltd.
|
* All Rights Reserved.
|
*
|
*/
|
|
/************************************
|
** This is an auto-generated file **
|
** DO NOT EDIT BELOW **
|
************************************/
|
|
#ifndef ASIC_REG_TPC7_CFG_REGS_H_
|
#define ASIC_REG_TPC7_CFG_REGS_H_
|
|
/*
|
*****************************************
|
* TPC7_CFG (Prototype: TPC)
|
*****************************************
|
*/
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC6418
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC641C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6420
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC6424
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6428
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC642C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6430
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6434
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC6438
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC643C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6440
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6444
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC6448
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC644C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6450
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC6454
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6458
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC645C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6460
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6464
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC6468
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC646C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6470
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC6474
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC6478
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC647C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC6480
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC6484
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC6488
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC648C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC6490
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC6494
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC6498
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC649C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64A0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64A4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64A8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64AC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64B0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64B4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64B8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64BC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC64C0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC64C4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC64C8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC64CC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC64D0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC64D4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC64D8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC64DC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC64E0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC64E4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC64E8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC64EC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC64F0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC64F4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC64F8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC64FC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6500
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC6504
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6508
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC650C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6510
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6514
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC6518
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC651C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6520
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6524
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC6528
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC652C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6530
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC6534
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC6538
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC653C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC6540
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC6544
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC6548
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC654C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC6550
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC6554
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC6558
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC655C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC6560
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC6564
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC6568
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC656C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC6570
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC6574
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC6578
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC657C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6580
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC6584
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6588
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC658C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC6590
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6594
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6598
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC659C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC65A0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC65A4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC65A8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC65AC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC65B0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC65B4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC65B8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC65BC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xFC65C0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xFC65C4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xFC65C8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xFC65CC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xFC65D0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xFC65D4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xFC65D8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xFC65DC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xFC65E0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xFC65E4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xFC65E8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xFC65EC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xFC65F0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xFC65F4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xFC65F8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xFC65FC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xFC6600
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xFC6604
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xFC6608
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xFC660C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xFC6610
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xFC6614
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xFC6618
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xFC661C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xFC6620
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xFC6624
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xFC6628
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xFC662C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xFC6630
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xFC6634
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xFC6638
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xFC663C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xFC6640
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xFC6644
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xFC6648
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xFC664C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xFC6650
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xFC6654
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xFC6658
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xFC665C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xFC6660
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xFC6664
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xFC6668
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xFC666C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xFC6670
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xFC6674
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xFC6678
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xFC667C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xFC6680
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xFC6684
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xFC6688
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xFC668C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xFC6690
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xFC6694
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xFC6698
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xFC669C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xFC66A0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xFC66A4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xFC66A8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xFC66AC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xFC66B0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xFC66B4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xFC66B8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xFC66BC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xFC66C0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xFC66C4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xFC66C8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xFC66CC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xFC66D0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xFC66D4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xFC66D8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xFC66DC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xFC66E0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xFC66E4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xFC66E8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xFC66EC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xFC66F0
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xFC66F4
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xFC66F8
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xFC66FC
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xFC6700
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xFC6704
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xFC6708
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xFC670C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xFC6710
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xFC6714
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xFC6718
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xFC671C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xFC6720
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xFC6724
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xFC6728
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xFC672C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xFC6730
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xFC6734
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xFC6738
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xFC673C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xFC6740
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xFC6744
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xFC6748
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xFC674C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xFC6750
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xFC6754
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xFC6758
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xFC675C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xFC6760
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xFC6764
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xFC6768
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xFC676C
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xFC6770
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xFC6774
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xFC6778
|
|
#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xFC677C
|
|
#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6780
|
|
#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR 0xFC6784
|
|
#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6788
|
|
#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC678C
|
|
#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6790
|
|
#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC6794
|
|
#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6798
|
|
#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC679C
|
|
#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC67A0
|
|
#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC67A4
|
|
#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC67A8
|
|
#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC67AC
|
|
#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC67B0
|
|
#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC67B4
|
|
#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC67B8
|
|
#define mmTPC7_CFG_KERNEL_KERNEL_ID 0xFC67BC
|
|
#define mmTPC7_CFG_KERNEL_SRF_0 0xFC67C0
|
|
#define mmTPC7_CFG_KERNEL_SRF_1 0xFC67C4
|
|
#define mmTPC7_CFG_KERNEL_SRF_2 0xFC67C8
|
|
#define mmTPC7_CFG_KERNEL_SRF_3 0xFC67CC
|
|
#define mmTPC7_CFG_KERNEL_SRF_4 0xFC67D0
|
|
#define mmTPC7_CFG_KERNEL_SRF_5 0xFC67D4
|
|
#define mmTPC7_CFG_KERNEL_SRF_6 0xFC67D8
|
|
#define mmTPC7_CFG_KERNEL_SRF_7 0xFC67DC
|
|
#define mmTPC7_CFG_KERNEL_SRF_8 0xFC67E0
|
|
#define mmTPC7_CFG_KERNEL_SRF_9 0xFC67E4
|
|
#define mmTPC7_CFG_KERNEL_SRF_10 0xFC67E8
|
|
#define mmTPC7_CFG_KERNEL_SRF_11 0xFC67EC
|
|
#define mmTPC7_CFG_KERNEL_SRF_12 0xFC67F0
|
|
#define mmTPC7_CFG_KERNEL_SRF_13 0xFC67F4
|
|
#define mmTPC7_CFG_KERNEL_SRF_14 0xFC67F8
|
|
#define mmTPC7_CFG_KERNEL_SRF_15 0xFC67FC
|
|
#define mmTPC7_CFG_KERNEL_SRF_16 0xFC6800
|
|
#define mmTPC7_CFG_KERNEL_SRF_17 0xFC6804
|
|
#define mmTPC7_CFG_KERNEL_SRF_18 0xFC6808
|
|
#define mmTPC7_CFG_KERNEL_SRF_19 0xFC680C
|
|
#define mmTPC7_CFG_KERNEL_SRF_20 0xFC6810
|
|
#define mmTPC7_CFG_KERNEL_SRF_21 0xFC6814
|
|
#define mmTPC7_CFG_KERNEL_SRF_22 0xFC6818
|
|
#define mmTPC7_CFG_KERNEL_SRF_23 0xFC681C
|
|
#define mmTPC7_CFG_KERNEL_SRF_24 0xFC6820
|
|
#define mmTPC7_CFG_KERNEL_SRF_25 0xFC6824
|
|
#define mmTPC7_CFG_KERNEL_SRF_26 0xFC6828
|
|
#define mmTPC7_CFG_KERNEL_SRF_27 0xFC682C
|
|
#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6830
|
|
#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6834
|
|
#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6838
|
|
#define mmTPC7_CFG_KERNEL_SRF_31 0xFC683C
|
|
#define mmTPC7_CFG_ROUND_CSR 0xFC68FC
|
|
#define mmTPC7_CFG_PROT 0xFC6900
|
|
#define mmTPC7_CFG_SEMAPHORE 0xFC6908
|
|
#define mmTPC7_CFG_VFLAGS 0xFC690C
|
|
#define mmTPC7_CFG_SFLAGS 0xFC6910
|
|
#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6918
|
|
#define mmTPC7_CFG_STATUS 0xFC691C
|
|
#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6920
|
|
#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6924
|
|
#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC692C
|
|
#define mmTPC7_CFG_TPC_CMD 0xFC6930
|
|
#define mmTPC7_CFG_TPC_EXECUTE 0xFC6938
|
|
#define mmTPC7_CFG_TPC_STALL 0xFC693C
|
|
#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6940
|
|
#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6944
|
|
#define mmTPC7_CFG_RD_RATE_LIMIT 0xFC6948
|
|
#define mmTPC7_CFG_WR_RATE_LIMIT 0xFC6950
|
|
#define mmTPC7_CFG_MSS_CONFIG 0xFC6954
|
|
#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6958
|
|
#define mmTPC7_CFG_TPC_INTR_MASK 0xFC695C
|
|
#define mmTPC7_CFG_WQ_CREDITS 0xFC6960
|
|
#define mmTPC7_CFG_ARUSER_LO 0xFC6964
|
|
#define mmTPC7_CFG_ARUSER_HI 0xFC6968
|
|
#define mmTPC7_CFG_AWUSER_LO 0xFC696C
|
|
#define mmTPC7_CFG_AWUSER_HI 0xFC6970
|
|
#define mmTPC7_CFG_OPCODE_EXEC 0xFC6974
|
|
#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO 0xFC6978
|
|
#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI 0xFC697C
|
|
#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO 0xFC6980
|
|
#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI 0xFC6984
|
|
#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO 0xFC6988
|
|
#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI 0xFC698C
|
|
#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO 0xFC6990
|
|
#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI 0xFC6994
|
|
#define mmTPC7_CFG_TSB_CFG_MAX_SIZE 0xFC6998
|
|
#define mmTPC7_CFG_TSB_CFG 0xFC699C
|
|
#define mmTPC7_CFG_DBGMEM_ADD 0xFC69A0
|
|
#define mmTPC7_CFG_DBGMEM_DATA_WR 0xFC69A4
|
|
#define mmTPC7_CFG_DBGMEM_DATA_RD 0xFC69A8
|
|
#define mmTPC7_CFG_DBGMEM_CTRL 0xFC69AC
|
|
#define mmTPC7_CFG_DBGMEM_RC 0xFC69B0
|
|
#define mmTPC7_CFG_TSB_INFLIGHT_CNTR 0xFC69B4
|
|
#define mmTPC7_CFG_WQ_INFLIGHT_CNTR 0xFC69B8
|
|
#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR 0xFC69BC
|
|
#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR 0xFC69C0
|
|
#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR 0xFC69C4
|
|
#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC69D0
|
|
#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC69D4
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC69D8
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC69DC
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC69E0
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC69E4
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC69E8
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC69EC
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC69F0
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC69F4
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC69F8
|
|
#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC69FC
|
|
#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00
|
|
#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04
|
|
#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08
|
|
#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A18
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A1C
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A20
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A24
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A28
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A2C
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A30
|
|
#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A34
|
|
#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A38
|
|
#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A3C
|
|
#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A40
|
|
#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A44
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A48
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A4C
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A50
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A54
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A58
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A5C
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A60
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A64
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A68
|
|
#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A6C
|
|
#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A70
|
|
#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A74
|
|
#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6A78
|
|
#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6A7C
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6A80
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6A84
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6A88
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6A8C
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6A90
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6A94
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6A98
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6A9C
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AA0
|
|
#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6AA4
|
|
#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AA8
|
|
#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AAC
|
|
#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AB0
|
|
#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AB4
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AB8
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6ABC
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6AC0
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6AC4
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6AC8
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6ACC
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6AD0
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6AD4
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6AD8
|
|
#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6ADC
|
|
#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6AE0
|
|
#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6AE4
|
|
#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6AE8
|
|
#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6AEC
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6AF0
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6AF4
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6AF8
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6AFC
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B00
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B04
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B08
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B0C
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B10
|
|
#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B14
|
|
#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B18
|
|
#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B1C
|
|
#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B20
|
|
#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B24
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B28
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B2C
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B30
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B34
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6B38
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6B3C
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6B40
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6B44
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6B48
|
|
#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6B4C
|
|
#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6B50
|
|
#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6B54
|
|
#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6B58
|
|
#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6B5C
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6B60
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6B64
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6B68
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6B6C
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6B70
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6B74
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6B78
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6B7C
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6B80
|
|
#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6B84
|
|
#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6B88
|
|
#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6B8C
|
|
#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6B90
|
|
#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6B94
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6B98
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6B9C
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6BA0
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6BA4
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6BA8
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6BAC
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6BB0
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6BB4
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6BB8
|
|
#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6BBC
|
|
#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xFC6BC0
|
|
#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xFC6BC4
|
|
#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE 0xFC6BC8
|
|
#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xFC6BCC
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE 0xFC6BD0
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xFC6BD4
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE 0xFC6BD8
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xFC6BDC
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE 0xFC6BE0
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xFC6BE4
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE 0xFC6BE8
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xFC6BEC
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE 0xFC6BF0
|
|
#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xFC6BF4
|
|
#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xFC6BF8
|
|
#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xFC6BFC
|
|
#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE 0xFC6C00
|
|
#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xFC6C04
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE 0xFC6C08
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xFC6C0C
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE 0xFC6C10
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xFC6C14
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE 0xFC6C18
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xFC6C1C
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE 0xFC6C20
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xFC6C24
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE 0xFC6C28
|
|
#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xFC6C2C
|
|
#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xFC6C30
|
|
#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xFC6C34
|
|
#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE 0xFC6C38
|
|
#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xFC6C3C
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE 0xFC6C40
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xFC6C44
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE 0xFC6C48
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xFC6C4C
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE 0xFC6C50
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xFC6C54
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE 0xFC6C58
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xFC6C5C
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE 0xFC6C60
|
|
#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xFC6C64
|
|
#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xFC6C68
|
|
#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xFC6C6C
|
|
#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE 0xFC6C70
|
|
#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xFC6C74
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE 0xFC6C78
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xFC6C7C
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE 0xFC6C80
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xFC6C84
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE 0xFC6C88
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xFC6C8C
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE 0xFC6C90
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xFC6C94
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE 0xFC6C98
|
|
#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xFC6C9C
|
|
#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xFC6CA0
|
|
#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xFC6CA4
|
|
#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE 0xFC6CA8
|
|
#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xFC6CAC
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE 0xFC6CB0
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xFC6CB4
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE 0xFC6CB8
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xFC6CBC
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE 0xFC6CC0
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xFC6CC4
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE 0xFC6CC8
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xFC6CCC
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE 0xFC6CD0
|
|
#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xFC6CD4
|
|
#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xFC6CD8
|
|
#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xFC6CDC
|
|
#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE 0xFC6CE0
|
|
#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xFC6CE4
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE 0xFC6CE8
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xFC6CEC
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE 0xFC6CF0
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xFC6CF4
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE 0xFC6CF8
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xFC6CFC
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE 0xFC6D00
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xFC6D04
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE 0xFC6D08
|
|
#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xFC6D0C
|
|
#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xFC6D10
|
|
#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xFC6D14
|
|
#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE 0xFC6D18
|
|
#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xFC6D1C
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE 0xFC6D20
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xFC6D24
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE 0xFC6D28
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xFC6D2C
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE 0xFC6D30
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xFC6D34
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE 0xFC6D38
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xFC6D3C
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE 0xFC6D40
|
|
#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xFC6D44
|
|
#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xFC6D48
|
|
#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xFC6D4C
|
|
#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE 0xFC6D50
|
|
#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xFC6D54
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE 0xFC6D58
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xFC6D5C
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE 0xFC6D60
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xFC6D64
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE 0xFC6D68
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xFC6D6C
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE 0xFC6D70
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xFC6D74
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE 0xFC6D78
|
|
#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xFC6D7C
|
|
#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D80
|
|
#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR 0xFC6D84
|
|
#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6D88
|
|
#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6D8C
|
|
#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6D90
|
|
#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6D94
|
|
#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6D98
|
|
#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6D9C
|
|
#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6DA0
|
|
#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6DA4
|
|
#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6DA8
|
|
#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6DAC
|
|
#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6DB0
|
|
#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6DB4
|
|
#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6DB8
|
|
#define mmTPC7_CFG_QM_KERNEL_ID 0xFC6DBC
|
|
#define mmTPC7_CFG_QM_SRF_0 0xFC6DC0
|
|
#define mmTPC7_CFG_QM_SRF_1 0xFC6DC4
|
|
#define mmTPC7_CFG_QM_SRF_2 0xFC6DC8
|
|
#define mmTPC7_CFG_QM_SRF_3 0xFC6DCC
|
|
#define mmTPC7_CFG_QM_SRF_4 0xFC6DD0
|
|
#define mmTPC7_CFG_QM_SRF_5 0xFC6DD4
|
|
#define mmTPC7_CFG_QM_SRF_6 0xFC6DD8
|
|
#define mmTPC7_CFG_QM_SRF_7 0xFC6DDC
|
|
#define mmTPC7_CFG_QM_SRF_8 0xFC6DE0
|
|
#define mmTPC7_CFG_QM_SRF_9 0xFC6DE4
|
|
#define mmTPC7_CFG_QM_SRF_10 0xFC6DE8
|
|
#define mmTPC7_CFG_QM_SRF_11 0xFC6DEC
|
|
#define mmTPC7_CFG_QM_SRF_12 0xFC6DF0
|
|
#define mmTPC7_CFG_QM_SRF_13 0xFC6DF4
|
|
#define mmTPC7_CFG_QM_SRF_14 0xFC6DF8
|
|
#define mmTPC7_CFG_QM_SRF_15 0xFC6DFC
|
|
#define mmTPC7_CFG_QM_SRF_16 0xFC6E00
|
|
#define mmTPC7_CFG_QM_SRF_17 0xFC6E04
|
|
#define mmTPC7_CFG_QM_SRF_18 0xFC6E08
|
|
#define mmTPC7_CFG_QM_SRF_19 0xFC6E0C
|
|
#define mmTPC7_CFG_QM_SRF_20 0xFC6E10
|
|
#define mmTPC7_CFG_QM_SRF_21 0xFC6E14
|
|
#define mmTPC7_CFG_QM_SRF_22 0xFC6E18
|
|
#define mmTPC7_CFG_QM_SRF_23 0xFC6E1C
|
|
#define mmTPC7_CFG_QM_SRF_24 0xFC6E20
|
|
#define mmTPC7_CFG_QM_SRF_25 0xFC6E24
|
|
#define mmTPC7_CFG_QM_SRF_26 0xFC6E28
|
|
#define mmTPC7_CFG_QM_SRF_27 0xFC6E2C
|
|
#define mmTPC7_CFG_QM_SRF_28 0xFC6E30
|
|
#define mmTPC7_CFG_QM_SRF_29 0xFC6E34
|
|
#define mmTPC7_CFG_QM_SRF_30 0xFC6E38
|
|
#define mmTPC7_CFG_QM_SRF_31 0xFC6E3C
|
|
#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */
|
