/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC5_QM_REGS_H_
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#define ASIC_REG_TPC5_QM_REGS_H_
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/*
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*****************************************
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* TPC5_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC5_QM_GLBL_CFG0 0xF48000
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#define mmTPC5_QM_GLBL_CFG1 0xF48004
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#define mmTPC5_QM_GLBL_PROT 0xF48008
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#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C
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#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010
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#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014
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#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018
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#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C
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#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020
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#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024
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#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028
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#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C
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#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030
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#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034
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#define mmTPC5_QM_GLBL_STS0 0xF48038
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#define mmTPC5_QM_GLBL_STS1_0 0xF48040
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#define mmTPC5_QM_GLBL_STS1_1 0xF48044
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#define mmTPC5_QM_GLBL_STS1_2 0xF48048
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#define mmTPC5_QM_GLBL_STS1_3 0xF4804C
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#define mmTPC5_QM_GLBL_STS1_4 0xF48050
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#define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054
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#define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058
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#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C
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#define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060
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#define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068
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#define mmTPC5_QM_PQ_BASE_LO_0 0xF48070
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#define mmTPC5_QM_PQ_BASE_LO_1 0xF48074
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#define mmTPC5_QM_PQ_BASE_LO_2 0xF48078
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#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C
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#define mmTPC5_QM_PQ_BASE_HI_0 0xF48080
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#define mmTPC5_QM_PQ_BASE_HI_1 0xF48084
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#define mmTPC5_QM_PQ_BASE_HI_2 0xF48088
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#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C
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#define mmTPC5_QM_PQ_SIZE_0 0xF48090
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#define mmTPC5_QM_PQ_SIZE_1 0xF48094
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#define mmTPC5_QM_PQ_SIZE_2 0xF48098
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#define mmTPC5_QM_PQ_SIZE_3 0xF4809C
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#define mmTPC5_QM_PQ_PI_0 0xF480A0
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#define mmTPC5_QM_PQ_PI_1 0xF480A4
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#define mmTPC5_QM_PQ_PI_2 0xF480A8
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#define mmTPC5_QM_PQ_PI_3 0xF480AC
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#define mmTPC5_QM_PQ_CI_0 0xF480B0
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#define mmTPC5_QM_PQ_CI_1 0xF480B4
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#define mmTPC5_QM_PQ_CI_2 0xF480B8
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#define mmTPC5_QM_PQ_CI_3 0xF480BC
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#define mmTPC5_QM_PQ_CFG0_0 0xF480C0
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#define mmTPC5_QM_PQ_CFG0_1 0xF480C4
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#define mmTPC5_QM_PQ_CFG0_2 0xF480C8
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#define mmTPC5_QM_PQ_CFG0_3 0xF480CC
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#define mmTPC5_QM_PQ_CFG1_0 0xF480D0
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#define mmTPC5_QM_PQ_CFG1_1 0xF480D4
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#define mmTPC5_QM_PQ_CFG1_2 0xF480D8
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#define mmTPC5_QM_PQ_CFG1_3 0xF480DC
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#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0
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#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4
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#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8
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#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC
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#define mmTPC5_QM_PQ_STS0_0 0xF480F0
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#define mmTPC5_QM_PQ_STS0_1 0xF480F4
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#define mmTPC5_QM_PQ_STS0_2 0xF480F8
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#define mmTPC5_QM_PQ_STS0_3 0xF480FC
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#define mmTPC5_QM_PQ_STS1_0 0xF48100
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#define mmTPC5_QM_PQ_STS1_1 0xF48104
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#define mmTPC5_QM_PQ_STS1_2 0xF48108
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#define mmTPC5_QM_PQ_STS1_3 0xF4810C
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#define mmTPC5_QM_CQ_CFG0_0 0xF48110
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#define mmTPC5_QM_CQ_CFG0_1 0xF48114
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#define mmTPC5_QM_CQ_CFG0_2 0xF48118
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#define mmTPC5_QM_CQ_CFG0_3 0xF4811C
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#define mmTPC5_QM_CQ_CFG0_4 0xF48120
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#define mmTPC5_QM_CQ_CFG1_0 0xF48124
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#define mmTPC5_QM_CQ_CFG1_1 0xF48128
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#define mmTPC5_QM_CQ_CFG1_2 0xF4812C
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#define mmTPC5_QM_CQ_CFG1_3 0xF48130
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#define mmTPC5_QM_CQ_CFG1_4 0xF48134
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#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138
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#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C
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#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140
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#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144
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#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148
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#define mmTPC5_QM_CQ_STS0_0 0xF4814C
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#define mmTPC5_QM_CQ_STS0_1 0xF48150
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#define mmTPC5_QM_CQ_STS0_2 0xF48154
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#define mmTPC5_QM_CQ_STS0_3 0xF48158
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#define mmTPC5_QM_CQ_STS0_4 0xF4815C
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#define mmTPC5_QM_CQ_STS1_0 0xF48160
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#define mmTPC5_QM_CQ_STS1_1 0xF48164
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#define mmTPC5_QM_CQ_STS1_2 0xF48168
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#define mmTPC5_QM_CQ_STS1_3 0xF4816C
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#define mmTPC5_QM_CQ_STS1_4 0xF48170
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#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174
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#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178
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#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C
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#define mmTPC5_QM_CQ_CTL_0 0xF48180
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#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184
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#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188
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#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C
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#define mmTPC5_QM_CQ_CTL_1 0xF48190
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#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194
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#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198
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#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C
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#define mmTPC5_QM_CQ_CTL_2 0xF481A0
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#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4
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#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8
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#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC
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#define mmTPC5_QM_CQ_CTL_3 0xF481B0
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#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4
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#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8
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#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC
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#define mmTPC5_QM_CQ_CTL_4 0xF481C0
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#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4
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#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8
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#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC
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#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0
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#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4
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#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8
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#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC
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#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0
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#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4
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#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8
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#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC
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#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0
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#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4
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#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8
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#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC
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#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200
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#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204
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#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208
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#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C
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#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210
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#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214
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#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218
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#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C
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#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220
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#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248
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#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270
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#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298
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#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0
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#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4
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#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8
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#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC
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#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0
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#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4
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#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8
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#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0
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#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4
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#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8
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#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC
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#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0
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#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4
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#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8
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#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC
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#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300
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#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304
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#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308
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#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C
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#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310
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#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314
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#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318
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#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C
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#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320
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#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324
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#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328
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#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C
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#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330
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#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334
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#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338
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#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C
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#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340
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#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344
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#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348
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#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C
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#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350
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#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354
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#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358
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#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C
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#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360
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#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364
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#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368
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#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C
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#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370
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#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374
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#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378
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#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C
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#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380
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#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384
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#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388
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#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C
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#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390
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#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394
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#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398
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#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C
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#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0
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#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4
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#define mmTPC5_QM_CP_STS_0 0xF483A8
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#define mmTPC5_QM_CP_STS_1 0xF483AC
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#define mmTPC5_QM_CP_STS_2 0xF483B0
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#define mmTPC5_QM_CP_STS_3 0xF483B4
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#define mmTPC5_QM_CP_STS_4 0xF483B8
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#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC
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#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0
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#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4
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#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8
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#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC
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#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0
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#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4
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#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8
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#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC
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#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0
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#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4
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#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8
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#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC
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#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400
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#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404
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#define mmTPC5_QM_CP_DBG_0_0 0xF48408
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#define mmTPC5_QM_CP_DBG_0_1 0xF4840C
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#define mmTPC5_QM_CP_DBG_0_2 0xF48410
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#define mmTPC5_QM_CP_DBG_0_3 0xF48414
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#define mmTPC5_QM_CP_DBG_0_4 0xF48418
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#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C
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#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420
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#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424
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#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428
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#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C
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#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430
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#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434
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#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438
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#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C
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#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440
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#define mmTPC5_QM_ARB_CFG_0 0xF48A00
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#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04
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#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08
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#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C
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#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10
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#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14
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#define mmTPC5_QM_ARB_CFG_1 0xF48A18
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98
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#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C
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#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C
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#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20
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#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28
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#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C
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#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34
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#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38
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#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C
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#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44
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#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48
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#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C
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#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50
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#define mmTPC5_QM_ARB_BASE_LO 0xF48B54
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#define mmTPC5_QM_ARB_BASE_HI 0xF48B58
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#define mmTPC5_QM_ARB_STATE_STS 0xF48B80
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#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84
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#define mmTPC5_QM_ARB_MSG_STS 0xF48B88
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#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C
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#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C
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#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0
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#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8
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#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0
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#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4
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#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8
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#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC
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#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0
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#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4
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#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8
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#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC
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#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0
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#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4
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#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8
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#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC
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#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0
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#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4
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#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8
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#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC
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#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0
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#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4
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#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8
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#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC
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#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00
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#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04
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#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08
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#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C
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#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10
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#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14
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#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18
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#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C
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#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20
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#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24
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#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28
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#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C
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#define mmTPC5_QM_CGM_CFG 0xF48C70
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#define mmTPC5_QM_CGM_STS 0xF48C74
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#define mmTPC5_QM_CGM_CFG1 0xF48C78
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#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80
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#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84
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#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90
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#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94
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#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98
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#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C
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#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0
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#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4
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#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0
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#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4
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#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8
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#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC
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#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0
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#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4
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#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8
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#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00
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#endif /* ASIC_REG_TPC5_QM_REGS_H_ */
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