/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC5_CFG_REGS_H_
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#define ASIC_REG_TPC5_CFG_REGS_H_
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/*
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*****************************************
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* TPC5_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400
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#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404
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#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408
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#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430
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#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434
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#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438
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#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C
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#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440
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#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468
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#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C
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#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470
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#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474
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#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478
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#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0
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#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4
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#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8
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#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC
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#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0
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#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8
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#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC
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#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0
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#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4
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#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8
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#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510
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#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514
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#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518
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#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C
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#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520
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#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548
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#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C
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#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550
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#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554
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#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558
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#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580
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#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584
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#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588
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#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C
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#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590
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#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8
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#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC
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#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0
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#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4
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#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8
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#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0
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#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4
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#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8
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#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC
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#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600
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#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628
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#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C
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#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630
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#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634
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#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638
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#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660
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#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664
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#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668
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#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C
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#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670
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#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698
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#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C
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#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0
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#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4
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#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8
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#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0
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#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4
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#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8
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#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC
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#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0
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#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708
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#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C
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#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710
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#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714
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#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718
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#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740
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#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744
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#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748
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#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C
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#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750
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#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778
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#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C
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#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780
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#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784
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#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788
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#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C
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#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790
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#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794
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#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798
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#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C
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#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0
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#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4
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#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8
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#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC
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#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0
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#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4
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#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8
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#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC
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#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0
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#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4
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#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8
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#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC
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#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0
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#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4
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#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8
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#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC
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#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0
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#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4
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#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8
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#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC
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#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0
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#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4
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#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8
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#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC
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#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800
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#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804
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#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808
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#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C
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#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810
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#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814
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#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818
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#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C
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#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820
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#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824
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#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828
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#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C
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#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830
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#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834
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#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838
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#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C
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#define mmTPC5_CFG_ROUND_CSR 0xF468FC
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#define mmTPC5_CFG_PROT 0xF46900
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#define mmTPC5_CFG_SEMAPHORE 0xF46908
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#define mmTPC5_CFG_VFLAGS 0xF4690C
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#define mmTPC5_CFG_SFLAGS 0xF46910
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#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918
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#define mmTPC5_CFG_STATUS 0xF4691C
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#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920
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#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924
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#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C
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#define mmTPC5_CFG_TPC_CMD 0xF46930
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#define mmTPC5_CFG_TPC_EXECUTE 0xF46938
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#define mmTPC5_CFG_TPC_STALL 0xF4693C
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#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940
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#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944
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#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948
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#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950
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#define mmTPC5_CFG_MSS_CONFIG 0xF46954
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#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958
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#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C
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#define mmTPC5_CFG_WQ_CREDITS 0xF46960
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#define mmTPC5_CFG_ARUSER_LO 0xF46964
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#define mmTPC5_CFG_ARUSER_HI 0xF46968
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#define mmTPC5_CFG_AWUSER_LO 0xF4696C
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#define mmTPC5_CFG_AWUSER_HI 0xF46970
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#define mmTPC5_CFG_OPCODE_EXEC 0xF46974
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#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978
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#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C
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#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980
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#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984
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#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988
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#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C
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#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990
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#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994
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#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998
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#define mmTPC5_CFG_TSB_CFG 0xF4699C
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#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0
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#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4
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#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8
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#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC
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#define mmTPC5_CFG_DBGMEM_RC 0xF469B0
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#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4
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#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8
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#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC
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#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0
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#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4
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#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0
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#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4
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#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8
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#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC
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#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0
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#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4
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#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8
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#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC
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#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0
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#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4
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#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8
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#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC
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#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00
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#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04
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#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08
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#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30
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#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34
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#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38
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#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C
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#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40
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#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68
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#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C
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#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70
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#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74
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#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78
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#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0
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#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4
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#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8
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#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC
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#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0
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#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8
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#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC
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#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0
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#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4
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#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8
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#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10
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#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14
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#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18
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#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C
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#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20
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#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48
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#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C
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#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50
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#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54
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#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58
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#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70
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|
#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C
|
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#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80
|
|
#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84
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#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88
|
|
#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C
|
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#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90
|
|
#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C
|
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#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8
|
|
#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC
|
|
#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0
|
|
#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4
|
|
#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8
|
|
#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0
|
|
#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4
|
|
#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8
|
|
#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC
|
|
#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00
|
|
#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20
|
|
#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24
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#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28
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#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C
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#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30
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#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34
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#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38
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#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60
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#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64
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#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68
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#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C
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#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70
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#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98
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#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C
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#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0
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#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4
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#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8
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#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0
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#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4
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#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8
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#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC
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#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0
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#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08
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#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C
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#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10
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#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14
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#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18
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#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40
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#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44
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#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48
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#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C
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#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50
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#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78
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#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C
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#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80
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#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84
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#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88
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#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C
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#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90
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#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94
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#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98
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#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C
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#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0
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#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4
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#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8
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#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC
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#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0
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#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4
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#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8
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#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC
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#define mmTPC5_CFG_QM_SRF_0 0xF46DC0
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#define mmTPC5_CFG_QM_SRF_1 0xF46DC4
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#define mmTPC5_CFG_QM_SRF_2 0xF46DC8
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#define mmTPC5_CFG_QM_SRF_3 0xF46DCC
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#define mmTPC5_CFG_QM_SRF_4 0xF46DD0
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#define mmTPC5_CFG_QM_SRF_5 0xF46DD4
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#define mmTPC5_CFG_QM_SRF_6 0xF46DD8
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#define mmTPC5_CFG_QM_SRF_7 0xF46DDC
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#define mmTPC5_CFG_QM_SRF_8 0xF46DE0
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#define mmTPC5_CFG_QM_SRF_9 0xF46DE4
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#define mmTPC5_CFG_QM_SRF_10 0xF46DE8
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#define mmTPC5_CFG_QM_SRF_11 0xF46DEC
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#define mmTPC5_CFG_QM_SRF_12 0xF46DF0
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#define mmTPC5_CFG_QM_SRF_13 0xF46DF4
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#define mmTPC5_CFG_QM_SRF_14 0xF46DF8
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#define mmTPC5_CFG_QM_SRF_15 0xF46DFC
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#define mmTPC5_CFG_QM_SRF_16 0xF46E00
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#define mmTPC5_CFG_QM_SRF_17 0xF46E04
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#define mmTPC5_CFG_QM_SRF_18 0xF46E08
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#define mmTPC5_CFG_QM_SRF_19 0xF46E0C
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#define mmTPC5_CFG_QM_SRF_20 0xF46E10
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#define mmTPC5_CFG_QM_SRF_21 0xF46E14
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#define mmTPC5_CFG_QM_SRF_22 0xF46E18
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#define mmTPC5_CFG_QM_SRF_23 0xF46E1C
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#define mmTPC5_CFG_QM_SRF_24 0xF46E20
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#define mmTPC5_CFG_QM_SRF_25 0xF46E24
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#define mmTPC5_CFG_QM_SRF_26 0xF46E28
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#define mmTPC5_CFG_QM_SRF_27 0xF46E2C
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#define mmTPC5_CFG_QM_SRF_28 0xF46E30
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#define mmTPC5_CFG_QM_SRF_29 0xF46E34
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#define mmTPC5_CFG_QM_SRF_30 0xF46E38
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#define mmTPC5_CFG_QM_SRF_31 0xF46E3C
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#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */
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