/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC2_QM_REGS_H_
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#define ASIC_REG_TPC2_QM_REGS_H_
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/*
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*****************************************
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* TPC2_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC2_QM_GLBL_CFG0 0xE88000
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#define mmTPC2_QM_GLBL_CFG1 0xE88004
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#define mmTPC2_QM_GLBL_PROT 0xE88008
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#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C
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#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010
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#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014
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#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018
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#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C
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#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020
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#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024
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#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028
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#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C
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#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030
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#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034
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#define mmTPC2_QM_GLBL_STS0 0xE88038
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#define mmTPC2_QM_GLBL_STS1_0 0xE88040
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#define mmTPC2_QM_GLBL_STS1_1 0xE88044
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#define mmTPC2_QM_GLBL_STS1_2 0xE88048
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#define mmTPC2_QM_GLBL_STS1_3 0xE8804C
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#define mmTPC2_QM_GLBL_STS1_4 0xE88050
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#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054
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#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058
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#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C
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#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060
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#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068
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#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070
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#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074
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#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078
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#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C
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#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080
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#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084
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#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088
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#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C
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#define mmTPC2_QM_PQ_SIZE_0 0xE88090
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#define mmTPC2_QM_PQ_SIZE_1 0xE88094
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#define mmTPC2_QM_PQ_SIZE_2 0xE88098
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#define mmTPC2_QM_PQ_SIZE_3 0xE8809C
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#define mmTPC2_QM_PQ_PI_0 0xE880A0
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#define mmTPC2_QM_PQ_PI_1 0xE880A4
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#define mmTPC2_QM_PQ_PI_2 0xE880A8
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#define mmTPC2_QM_PQ_PI_3 0xE880AC
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#define mmTPC2_QM_PQ_CI_0 0xE880B0
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#define mmTPC2_QM_PQ_CI_1 0xE880B4
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#define mmTPC2_QM_PQ_CI_2 0xE880B8
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#define mmTPC2_QM_PQ_CI_3 0xE880BC
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#define mmTPC2_QM_PQ_CFG0_0 0xE880C0
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#define mmTPC2_QM_PQ_CFG0_1 0xE880C4
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#define mmTPC2_QM_PQ_CFG0_2 0xE880C8
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#define mmTPC2_QM_PQ_CFG0_3 0xE880CC
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#define mmTPC2_QM_PQ_CFG1_0 0xE880D0
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#define mmTPC2_QM_PQ_CFG1_1 0xE880D4
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#define mmTPC2_QM_PQ_CFG1_2 0xE880D8
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#define mmTPC2_QM_PQ_CFG1_3 0xE880DC
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#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0
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#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4
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#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8
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#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC
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#define mmTPC2_QM_PQ_STS0_0 0xE880F0
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#define mmTPC2_QM_PQ_STS0_1 0xE880F4
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#define mmTPC2_QM_PQ_STS0_2 0xE880F8
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#define mmTPC2_QM_PQ_STS0_3 0xE880FC
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#define mmTPC2_QM_PQ_STS1_0 0xE88100
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#define mmTPC2_QM_PQ_STS1_1 0xE88104
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#define mmTPC2_QM_PQ_STS1_2 0xE88108
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#define mmTPC2_QM_PQ_STS1_3 0xE8810C
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#define mmTPC2_QM_CQ_CFG0_0 0xE88110
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#define mmTPC2_QM_CQ_CFG0_1 0xE88114
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#define mmTPC2_QM_CQ_CFG0_2 0xE88118
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#define mmTPC2_QM_CQ_CFG0_3 0xE8811C
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#define mmTPC2_QM_CQ_CFG0_4 0xE88120
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#define mmTPC2_QM_CQ_CFG1_0 0xE88124
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#define mmTPC2_QM_CQ_CFG1_1 0xE88128
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#define mmTPC2_QM_CQ_CFG1_2 0xE8812C
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#define mmTPC2_QM_CQ_CFG1_3 0xE88130
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#define mmTPC2_QM_CQ_CFG1_4 0xE88134
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#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138
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#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C
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#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140
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#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144
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#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148
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#define mmTPC2_QM_CQ_STS0_0 0xE8814C
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#define mmTPC2_QM_CQ_STS0_1 0xE88150
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#define mmTPC2_QM_CQ_STS0_2 0xE88154
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#define mmTPC2_QM_CQ_STS0_3 0xE88158
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#define mmTPC2_QM_CQ_STS0_4 0xE8815C
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#define mmTPC2_QM_CQ_STS1_0 0xE88160
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#define mmTPC2_QM_CQ_STS1_1 0xE88164
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#define mmTPC2_QM_CQ_STS1_2 0xE88168
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#define mmTPC2_QM_CQ_STS1_3 0xE8816C
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#define mmTPC2_QM_CQ_STS1_4 0xE88170
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#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174
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#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178
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#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C
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#define mmTPC2_QM_CQ_CTL_0 0xE88180
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#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184
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#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188
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#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C
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#define mmTPC2_QM_CQ_CTL_1 0xE88190
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#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194
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#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198
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#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C
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#define mmTPC2_QM_CQ_CTL_2 0xE881A0
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#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4
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#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8
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#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC
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#define mmTPC2_QM_CQ_CTL_3 0xE881B0
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#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4
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#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8
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#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC
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#define mmTPC2_QM_CQ_CTL_4 0xE881C0
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#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4
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#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8
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#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC
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#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0
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#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4
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#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8
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#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC
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#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0
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#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4
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#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8
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#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC
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#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0
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#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4
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#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8
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#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC
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#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200
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#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204
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#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208
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#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C
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#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210
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#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214
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#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218
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#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C
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#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220
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#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248
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#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270
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#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298
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#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0
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#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4
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#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8
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#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC
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#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0
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#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4
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#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8
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#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0
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#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4
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#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8
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#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC
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#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0
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#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4
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#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8
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#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC
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#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300
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#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304
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#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308
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#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C
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#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310
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#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314
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#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318
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#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C
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#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320
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#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324
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#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328
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#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C
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#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330
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#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334
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#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338
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#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C
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#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340
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#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344
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#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348
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#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C
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#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350
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#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354
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#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358
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#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C
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#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360
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#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364
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#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368
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#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C
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#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370
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#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374
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#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378
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#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C
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#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380
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#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384
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#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388
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#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C
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#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390
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#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394
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#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398
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#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C
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#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0
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#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4
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#define mmTPC2_QM_CP_STS_0 0xE883A8
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#define mmTPC2_QM_CP_STS_1 0xE883AC
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#define mmTPC2_QM_CP_STS_2 0xE883B0
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#define mmTPC2_QM_CP_STS_3 0xE883B4
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#define mmTPC2_QM_CP_STS_4 0xE883B8
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#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC
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#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0
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#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4
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#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8
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#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC
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#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0
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#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4
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#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8
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#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC
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#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0
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#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4
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#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8
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#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC
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#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400
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#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404
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#define mmTPC2_QM_CP_DBG_0_0 0xE88408
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#define mmTPC2_QM_CP_DBG_0_1 0xE8840C
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#define mmTPC2_QM_CP_DBG_0_2 0xE88410
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#define mmTPC2_QM_CP_DBG_0_3 0xE88414
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#define mmTPC2_QM_CP_DBG_0_4 0xE88418
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#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C
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#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420
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#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424
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#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428
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#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C
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#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430
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#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434
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#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438
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#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C
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#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440
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#define mmTPC2_QM_ARB_CFG_0 0xE88A00
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#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04
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#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08
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#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C
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#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10
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#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14
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#define mmTPC2_QM_ARB_CFG_1 0xE88A18
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98
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#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C
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#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C
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#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20
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#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28
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#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C
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#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34
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#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38
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#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C
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#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44
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#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48
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#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C
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#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50
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#define mmTPC2_QM_ARB_BASE_LO 0xE88B54
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#define mmTPC2_QM_ARB_BASE_HI 0xE88B58
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#define mmTPC2_QM_ARB_STATE_STS 0xE88B80
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#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84
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#define mmTPC2_QM_ARB_MSG_STS 0xE88B88
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#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C
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#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C
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#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0
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#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8
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#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0
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#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4
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#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8
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#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC
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#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0
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#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4
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#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8
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#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC
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#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0
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#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4
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#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8
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#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC
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#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0
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#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4
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#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8
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#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC
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#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0
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#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4
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#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8
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#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC
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#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00
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#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04
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#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08
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#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C
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#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10
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#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14
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#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18
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#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C
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#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20
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#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24
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#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28
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#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C
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#define mmTPC2_QM_CGM_CFG 0xE88C70
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#define mmTPC2_QM_CGM_STS 0xE88C74
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#define mmTPC2_QM_CGM_CFG1 0xE88C78
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#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80
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#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84
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#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90
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#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94
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#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98
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#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C
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#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0
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#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4
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#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0
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#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4
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#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8
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#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC
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#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0
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#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4
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#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8
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#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00
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#endif /* ASIC_REG_TPC2_QM_REGS_H_ */
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