/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC1_QM_REGS_H_
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#define ASIC_REG_TPC1_QM_REGS_H_
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/*
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*****************************************
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* TPC1_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC1_QM_GLBL_CFG0 0xE48000
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#define mmTPC1_QM_GLBL_CFG1 0xE48004
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#define mmTPC1_QM_GLBL_PROT 0xE48008
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#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C
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#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010
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#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014
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#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018
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#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C
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#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020
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#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024
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#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028
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#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C
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#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030
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#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034
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#define mmTPC1_QM_GLBL_STS0 0xE48038
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#define mmTPC1_QM_GLBL_STS1_0 0xE48040
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#define mmTPC1_QM_GLBL_STS1_1 0xE48044
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#define mmTPC1_QM_GLBL_STS1_2 0xE48048
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#define mmTPC1_QM_GLBL_STS1_3 0xE4804C
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#define mmTPC1_QM_GLBL_STS1_4 0xE48050
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#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054
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#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058
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#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C
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#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060
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#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068
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#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070
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#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074
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#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078
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#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C
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#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080
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#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084
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#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088
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#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C
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#define mmTPC1_QM_PQ_SIZE_0 0xE48090
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#define mmTPC1_QM_PQ_SIZE_1 0xE48094
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#define mmTPC1_QM_PQ_SIZE_2 0xE48098
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#define mmTPC1_QM_PQ_SIZE_3 0xE4809C
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#define mmTPC1_QM_PQ_PI_0 0xE480A0
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#define mmTPC1_QM_PQ_PI_1 0xE480A4
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#define mmTPC1_QM_PQ_PI_2 0xE480A8
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#define mmTPC1_QM_PQ_PI_3 0xE480AC
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#define mmTPC1_QM_PQ_CI_0 0xE480B0
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#define mmTPC1_QM_PQ_CI_1 0xE480B4
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#define mmTPC1_QM_PQ_CI_2 0xE480B8
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#define mmTPC1_QM_PQ_CI_3 0xE480BC
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#define mmTPC1_QM_PQ_CFG0_0 0xE480C0
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#define mmTPC1_QM_PQ_CFG0_1 0xE480C4
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#define mmTPC1_QM_PQ_CFG0_2 0xE480C8
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#define mmTPC1_QM_PQ_CFG0_3 0xE480CC
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#define mmTPC1_QM_PQ_CFG1_0 0xE480D0
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#define mmTPC1_QM_PQ_CFG1_1 0xE480D4
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#define mmTPC1_QM_PQ_CFG1_2 0xE480D8
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#define mmTPC1_QM_PQ_CFG1_3 0xE480DC
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#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0
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#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4
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#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8
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#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC
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#define mmTPC1_QM_PQ_STS0_0 0xE480F0
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#define mmTPC1_QM_PQ_STS0_1 0xE480F4
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#define mmTPC1_QM_PQ_STS0_2 0xE480F8
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#define mmTPC1_QM_PQ_STS0_3 0xE480FC
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#define mmTPC1_QM_PQ_STS1_0 0xE48100
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#define mmTPC1_QM_PQ_STS1_1 0xE48104
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#define mmTPC1_QM_PQ_STS1_2 0xE48108
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#define mmTPC1_QM_PQ_STS1_3 0xE4810C
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#define mmTPC1_QM_CQ_CFG0_0 0xE48110
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#define mmTPC1_QM_CQ_CFG0_1 0xE48114
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#define mmTPC1_QM_CQ_CFG0_2 0xE48118
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#define mmTPC1_QM_CQ_CFG0_3 0xE4811C
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#define mmTPC1_QM_CQ_CFG0_4 0xE48120
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#define mmTPC1_QM_CQ_CFG1_0 0xE48124
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#define mmTPC1_QM_CQ_CFG1_1 0xE48128
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#define mmTPC1_QM_CQ_CFG1_2 0xE4812C
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#define mmTPC1_QM_CQ_CFG1_3 0xE48130
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#define mmTPC1_QM_CQ_CFG1_4 0xE48134
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#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138
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#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C
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#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140
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#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144
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#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148
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#define mmTPC1_QM_CQ_STS0_0 0xE4814C
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#define mmTPC1_QM_CQ_STS0_1 0xE48150
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#define mmTPC1_QM_CQ_STS0_2 0xE48154
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#define mmTPC1_QM_CQ_STS0_3 0xE48158
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#define mmTPC1_QM_CQ_STS0_4 0xE4815C
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#define mmTPC1_QM_CQ_STS1_0 0xE48160
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#define mmTPC1_QM_CQ_STS1_1 0xE48164
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#define mmTPC1_QM_CQ_STS1_2 0xE48168
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#define mmTPC1_QM_CQ_STS1_3 0xE4816C
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#define mmTPC1_QM_CQ_STS1_4 0xE48170
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#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174
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#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178
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#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C
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#define mmTPC1_QM_CQ_CTL_0 0xE48180
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#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184
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#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188
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#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C
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#define mmTPC1_QM_CQ_CTL_1 0xE48190
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#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194
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#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198
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#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C
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#define mmTPC1_QM_CQ_CTL_2 0xE481A0
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#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4
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#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8
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#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC
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#define mmTPC1_QM_CQ_CTL_3 0xE481B0
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#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4
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#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8
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#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC
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#define mmTPC1_QM_CQ_CTL_4 0xE481C0
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#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4
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#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8
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#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC
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#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0
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#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4
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#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8
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#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC
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#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0
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#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4
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#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8
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#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC
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#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0
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#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4
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#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8
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#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC
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#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200
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#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204
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#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208
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#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C
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#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210
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#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214
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#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218
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#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C
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#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220
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#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248
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#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270
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#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298
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#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0
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#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4
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#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8
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#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC
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#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0
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#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4
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#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8
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#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0
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#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4
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#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8
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#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC
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#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0
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#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4
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#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8
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#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC
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#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300
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#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304
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#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308
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#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C
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#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310
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#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314
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#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318
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#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C
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#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320
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#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324
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#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328
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#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C
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#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330
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#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334
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#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338
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#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C
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#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340
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#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344
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#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348
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#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C
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#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350
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#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354
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#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358
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#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C
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#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360
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#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364
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#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368
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#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C
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#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370
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#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374
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#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378
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#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C
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#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380
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#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384
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#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388
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#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C
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#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390
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#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394
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#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398
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#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C
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#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0
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#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4
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#define mmTPC1_QM_CP_STS_0 0xE483A8
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#define mmTPC1_QM_CP_STS_1 0xE483AC
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#define mmTPC1_QM_CP_STS_2 0xE483B0
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#define mmTPC1_QM_CP_STS_3 0xE483B4
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#define mmTPC1_QM_CP_STS_4 0xE483B8
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#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC
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#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0
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#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4
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#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8
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#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC
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#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0
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#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4
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#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8
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#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC
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#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0
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#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4
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#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8
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#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC
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#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400
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#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404
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#define mmTPC1_QM_CP_DBG_0_0 0xE48408
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#define mmTPC1_QM_CP_DBG_0_1 0xE4840C
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#define mmTPC1_QM_CP_DBG_0_2 0xE48410
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#define mmTPC1_QM_CP_DBG_0_3 0xE48414
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#define mmTPC1_QM_CP_DBG_0_4 0xE48418
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#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C
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#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420
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#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424
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#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428
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#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C
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#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430
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#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434
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#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438
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#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C
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#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440
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#define mmTPC1_QM_ARB_CFG_0 0xE48A00
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#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04
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#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08
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#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C
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#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10
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#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14
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#define mmTPC1_QM_ARB_CFG_1 0xE48A18
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98
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#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C
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#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C
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#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20
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#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28
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#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C
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#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34
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#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38
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#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C
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#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44
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#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48
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#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C
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#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50
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#define mmTPC1_QM_ARB_BASE_LO 0xE48B54
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#define mmTPC1_QM_ARB_BASE_HI 0xE48B58
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#define mmTPC1_QM_ARB_STATE_STS 0xE48B80
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#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84
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#define mmTPC1_QM_ARB_MSG_STS 0xE48B88
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#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C
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#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C
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#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0
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#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8
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#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0
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#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4
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#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8
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#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC
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#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0
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#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4
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#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8
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#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC
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#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0
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#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4
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#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8
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#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC
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#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0
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#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4
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#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8
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#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC
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#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0
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#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4
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#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8
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#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC
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#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00
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#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04
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#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08
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#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C
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#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10
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#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14
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#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18
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#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C
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#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20
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#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24
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#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28
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#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C
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#define mmTPC1_QM_CGM_CFG 0xE48C70
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#define mmTPC1_QM_CGM_STS 0xE48C74
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#define mmTPC1_QM_CGM_CFG1 0xE48C78
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#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80
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#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84
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#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90
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#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94
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#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98
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#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C
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#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0
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#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4
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#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0
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#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4
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#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8
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#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC
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#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0
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#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4
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#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8
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#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00
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#endif /* ASIC_REG_TPC1_QM_REGS_H_ */
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