/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC0_QM_REGS_H_
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#define ASIC_REG_TPC0_QM_REGS_H_
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/*
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*****************************************
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* TPC0_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC0_QM_GLBL_CFG0 0xE08000
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#define mmTPC0_QM_GLBL_CFG1 0xE08004
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#define mmTPC0_QM_GLBL_PROT 0xE08008
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#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C
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#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010
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#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014
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#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018
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#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C
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#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030
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#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034
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#define mmTPC0_QM_GLBL_STS0 0xE08038
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#define mmTPC0_QM_GLBL_STS1_0 0xE08040
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#define mmTPC0_QM_GLBL_STS1_1 0xE08044
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#define mmTPC0_QM_GLBL_STS1_2 0xE08048
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#define mmTPC0_QM_GLBL_STS1_3 0xE0804C
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#define mmTPC0_QM_GLBL_STS1_4 0xE08050
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#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054
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#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058
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#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C
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#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060
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#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068
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#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070
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#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074
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#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078
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#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C
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#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080
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#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084
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#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088
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#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C
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#define mmTPC0_QM_PQ_SIZE_0 0xE08090
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#define mmTPC0_QM_PQ_SIZE_1 0xE08094
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#define mmTPC0_QM_PQ_SIZE_2 0xE08098
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#define mmTPC0_QM_PQ_SIZE_3 0xE0809C
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#define mmTPC0_QM_PQ_PI_0 0xE080A0
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#define mmTPC0_QM_PQ_PI_1 0xE080A4
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#define mmTPC0_QM_PQ_PI_2 0xE080A8
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#define mmTPC0_QM_PQ_PI_3 0xE080AC
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#define mmTPC0_QM_PQ_CI_0 0xE080B0
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#define mmTPC0_QM_PQ_CI_1 0xE080B4
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#define mmTPC0_QM_PQ_CI_2 0xE080B8
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#define mmTPC0_QM_PQ_CI_3 0xE080BC
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#define mmTPC0_QM_PQ_CFG0_0 0xE080C0
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#define mmTPC0_QM_PQ_CFG0_1 0xE080C4
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#define mmTPC0_QM_PQ_CFG0_2 0xE080C8
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#define mmTPC0_QM_PQ_CFG0_3 0xE080CC
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#define mmTPC0_QM_PQ_CFG1_0 0xE080D0
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#define mmTPC0_QM_PQ_CFG1_1 0xE080D4
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#define mmTPC0_QM_PQ_CFG1_2 0xE080D8
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#define mmTPC0_QM_PQ_CFG1_3 0xE080DC
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#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0
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#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4
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#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8
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#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC
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#define mmTPC0_QM_PQ_STS0_0 0xE080F0
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#define mmTPC0_QM_PQ_STS0_1 0xE080F4
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#define mmTPC0_QM_PQ_STS0_2 0xE080F8
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#define mmTPC0_QM_PQ_STS0_3 0xE080FC
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#define mmTPC0_QM_PQ_STS1_0 0xE08100
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#define mmTPC0_QM_PQ_STS1_1 0xE08104
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#define mmTPC0_QM_PQ_STS1_2 0xE08108
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#define mmTPC0_QM_PQ_STS1_3 0xE0810C
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#define mmTPC0_QM_CQ_CFG0_0 0xE08110
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#define mmTPC0_QM_CQ_CFG0_1 0xE08114
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#define mmTPC0_QM_CQ_CFG0_2 0xE08118
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#define mmTPC0_QM_CQ_CFG0_3 0xE0811C
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#define mmTPC0_QM_CQ_CFG0_4 0xE08120
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#define mmTPC0_QM_CQ_CFG1_0 0xE08124
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#define mmTPC0_QM_CQ_CFG1_1 0xE08128
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#define mmTPC0_QM_CQ_CFG1_2 0xE0812C
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#define mmTPC0_QM_CQ_CFG1_3 0xE08130
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#define mmTPC0_QM_CQ_CFG1_4 0xE08134
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#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138
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#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C
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#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140
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#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144
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#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148
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#define mmTPC0_QM_CQ_STS0_0 0xE0814C
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#define mmTPC0_QM_CQ_STS0_1 0xE08150
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#define mmTPC0_QM_CQ_STS0_2 0xE08154
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#define mmTPC0_QM_CQ_STS0_3 0xE08158
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#define mmTPC0_QM_CQ_STS0_4 0xE0815C
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#define mmTPC0_QM_CQ_STS1_0 0xE08160
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#define mmTPC0_QM_CQ_STS1_1 0xE08164
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#define mmTPC0_QM_CQ_STS1_2 0xE08168
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#define mmTPC0_QM_CQ_STS1_3 0xE0816C
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#define mmTPC0_QM_CQ_STS1_4 0xE08170
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#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174
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#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178
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#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C
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#define mmTPC0_QM_CQ_CTL_0 0xE08180
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#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184
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#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188
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#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C
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#define mmTPC0_QM_CQ_CTL_1 0xE08190
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#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194
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#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198
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#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C
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#define mmTPC0_QM_CQ_CTL_2 0xE081A0
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#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4
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#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8
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#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC
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#define mmTPC0_QM_CQ_CTL_3 0xE081B0
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#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4
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#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8
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#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC
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#define mmTPC0_QM_CQ_CTL_4 0xE081C0
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#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4
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#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8
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#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC
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#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0
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#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4
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#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8
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#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC
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#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0
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#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4
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#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8
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#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC
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#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0
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#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4
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#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8
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#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC
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#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200
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#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204
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#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208
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#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C
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#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210
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#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214
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#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218
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#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C
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#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220
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#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248
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#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270
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#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298
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#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0
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#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4
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#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC
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#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300
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#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304
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#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308
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#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C
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#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310
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#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314
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#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318
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#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C
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#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320
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#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324
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#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328
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#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C
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#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330
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#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334
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#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338
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#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C
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#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340
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#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344
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#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348
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#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C
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#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350
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#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354
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#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358
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#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C
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#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360
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#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364
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#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368
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#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C
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#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370
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#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374
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#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378
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#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C
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#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380
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#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384
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#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388
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#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C
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#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390
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#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394
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#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398
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#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C
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#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0
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#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4
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#define mmTPC0_QM_CP_STS_0 0xE083A8
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#define mmTPC0_QM_CP_STS_1 0xE083AC
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#define mmTPC0_QM_CP_STS_2 0xE083B0
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#define mmTPC0_QM_CP_STS_3 0xE083B4
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#define mmTPC0_QM_CP_STS_4 0xE083B8
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#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC
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#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0
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#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4
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#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8
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#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC
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#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0
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#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4
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#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8
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#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC
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#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0
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#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4
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#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8
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#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC
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#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400
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#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404
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#define mmTPC0_QM_CP_DBG_0_0 0xE08408
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#define mmTPC0_QM_CP_DBG_0_1 0xE0840C
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#define mmTPC0_QM_CP_DBG_0_2 0xE08410
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#define mmTPC0_QM_CP_DBG_0_3 0xE08414
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#define mmTPC0_QM_CP_DBG_0_4 0xE08418
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#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C
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#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420
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#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424
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#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428
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#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C
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#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430
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#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434
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#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438
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#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C
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#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440
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#define mmTPC0_QM_ARB_CFG_0 0xE08A00
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#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04
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#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08
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#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C
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#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10
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#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14
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#define mmTPC0_QM_ARB_CFG_1 0xE08A18
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98
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#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C
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#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C
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#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20
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#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28
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#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C
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#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34
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#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38
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#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C
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#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44
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#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48
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#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C
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#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50
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#define mmTPC0_QM_ARB_BASE_LO 0xE08B54
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#define mmTPC0_QM_ARB_BASE_HI 0xE08B58
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#define mmTPC0_QM_ARB_STATE_STS 0xE08B80
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#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84
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#define mmTPC0_QM_ARB_MSG_STS 0xE08B88
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#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C
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#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C
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#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0
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#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8
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#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0
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#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4
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#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8
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#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC
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#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0
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#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4
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#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8
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#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC
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#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0
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#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4
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#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8
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#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC
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#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0
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#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4
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#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8
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#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC
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#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0
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#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4
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#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8
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#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC
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#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00
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#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04
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#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08
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#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C
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#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10
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#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14
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#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18
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#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C
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#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20
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#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24
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#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28
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#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C
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#define mmTPC0_QM_CGM_CFG 0xE08C70
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#define mmTPC0_QM_CGM_STS 0xE08C74
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#define mmTPC0_QM_CGM_CFG1 0xE08C78
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#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80
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#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84
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#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90
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#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94
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#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98
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#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C
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#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0
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#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4
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#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0
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#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4
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#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8
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#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC
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#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0
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#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4
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#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8
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#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00
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#endif /* ASIC_REG_TPC0_QM_REGS_H_ */
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