/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC0_CFG_REGS_H_
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#define ASIC_REG_TPC0_CFG_REGS_H_
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/*
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*****************************************
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* TPC0_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400
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#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404
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#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408
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#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430
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#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434
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#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438
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#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C
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#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440
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#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468
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#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C
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#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470
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#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474
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#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478
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#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0
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#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4
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#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8
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#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC
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#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0
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#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8
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#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC
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#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0
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#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4
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#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8
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#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510
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#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514
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#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518
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#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C
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#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520
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#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548
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#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C
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#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550
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#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554
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#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558
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#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580
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#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584
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#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588
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#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C
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#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590
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#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8
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#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC
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#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0
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#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4
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#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8
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#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0
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#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4
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#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8
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#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC
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#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600
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#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628
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#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C
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#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630
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#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634
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#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638
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#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660
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#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664
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#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668
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#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C
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#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670
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#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698
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#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C
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#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0
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#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4
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#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8
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#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0
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#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4
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#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8
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#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC
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#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0
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#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708
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#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C
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#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710
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#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714
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#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718
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#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740
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#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744
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#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748
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#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C
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#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750
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#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778
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#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C
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#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780
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#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784
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#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788
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#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C
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#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790
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#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794
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#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798
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#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C
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#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0
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#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4
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#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8
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#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC
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#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0
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#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4
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#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8
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#define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC
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#define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0
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#define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4
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#define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8
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#define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC
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#define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0
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#define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4
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#define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8
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#define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC
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#define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0
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#define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4
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#define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8
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#define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC
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#define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0
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#define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4
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#define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8
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#define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC
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#define mmTPC0_CFG_KERNEL_SRF_16 0xE06800
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#define mmTPC0_CFG_KERNEL_SRF_17 0xE06804
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#define mmTPC0_CFG_KERNEL_SRF_18 0xE06808
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#define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C
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#define mmTPC0_CFG_KERNEL_SRF_20 0xE06810
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#define mmTPC0_CFG_KERNEL_SRF_21 0xE06814
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#define mmTPC0_CFG_KERNEL_SRF_22 0xE06818
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#define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C
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#define mmTPC0_CFG_KERNEL_SRF_24 0xE06820
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#define mmTPC0_CFG_KERNEL_SRF_25 0xE06824
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#define mmTPC0_CFG_KERNEL_SRF_26 0xE06828
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#define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C
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#define mmTPC0_CFG_KERNEL_SRF_28 0xE06830
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#define mmTPC0_CFG_KERNEL_SRF_29 0xE06834
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#define mmTPC0_CFG_KERNEL_SRF_30 0xE06838
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#define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C
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#define mmTPC0_CFG_ROUND_CSR 0xE068FC
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#define mmTPC0_CFG_PROT 0xE06900
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#define mmTPC0_CFG_SEMAPHORE 0xE06908
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#define mmTPC0_CFG_VFLAGS 0xE0690C
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#define mmTPC0_CFG_SFLAGS 0xE06910
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#define mmTPC0_CFG_LFSR_POLYNOM 0xE06918
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#define mmTPC0_CFG_STATUS 0xE0691C
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#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920
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#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924
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#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C
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#define mmTPC0_CFG_TPC_CMD 0xE06930
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#define mmTPC0_CFG_TPC_EXECUTE 0xE06938
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#define mmTPC0_CFG_TPC_STALL 0xE0693C
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#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940
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#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944
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#define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948
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#define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950
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#define mmTPC0_CFG_MSS_CONFIG 0xE06954
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#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958
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#define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C
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#define mmTPC0_CFG_WQ_CREDITS 0xE06960
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#define mmTPC0_CFG_ARUSER_LO 0xE06964
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#define mmTPC0_CFG_ARUSER_HI 0xE06968
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#define mmTPC0_CFG_AWUSER_LO 0xE0696C
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#define mmTPC0_CFG_AWUSER_HI 0xE06970
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#define mmTPC0_CFG_OPCODE_EXEC 0xE06974
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#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978
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#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C
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#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980
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#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984
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#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988
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#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C
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#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990
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#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994
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#define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998
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#define mmTPC0_CFG_TSB_CFG 0xE0699C
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#define mmTPC0_CFG_DBGMEM_ADD 0xE069A0
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#define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4
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#define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8
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#define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC
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#define mmTPC0_CFG_DBGMEM_RC 0xE069B0
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#define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4
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#define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8
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#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC
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#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0
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#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4
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#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0
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#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4
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#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8
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#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC
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#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0
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#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4
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#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8
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#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC
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#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0
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#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4
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#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8
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#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC
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#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00
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#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04
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#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08
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#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30
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#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34
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#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38
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#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C
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#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40
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#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68
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#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C
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#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70
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#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74
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#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78
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#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0
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#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4
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#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8
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#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC
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#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0
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#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4
|
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8
|
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#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC
|
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#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0
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#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4
|
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#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8
|
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#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10
|
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#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14
|
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#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18
|
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#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C
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#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20
|
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#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C
|
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#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40
|
|
#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44
|
|
#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48
|
|
#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C
|
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#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50
|
|
#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54
|
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#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58
|
|
#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C
|
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#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80
|
|
#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84
|
|
#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88
|
|
#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C
|
|
#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90
|
|
#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8
|
|
#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC
|
|
#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0
|
|
#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4
|
|
#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8
|
|
#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0
|
|
#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4
|
|
#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8
|
|
#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC
|
|
#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00
|
|
#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20
|
|
#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24
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#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28
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#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C
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#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30
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#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34
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#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38
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#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60
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#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64
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#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68
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#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C
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#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70
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#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98
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#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C
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#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0
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#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4
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#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8
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#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0
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#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4
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#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8
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#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC
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#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0
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#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08
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#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C
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#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10
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#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14
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#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18
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#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40
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#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44
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#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48
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#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C
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#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50
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#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78
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#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C
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#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80
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#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84
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#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88
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#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C
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#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90
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#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94
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#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98
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#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C
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#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0
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#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4
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#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8
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#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC
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#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0
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#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4
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#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8
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#define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC
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#define mmTPC0_CFG_QM_SRF_0 0xE06DC0
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#define mmTPC0_CFG_QM_SRF_1 0xE06DC4
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#define mmTPC0_CFG_QM_SRF_2 0xE06DC8
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#define mmTPC0_CFG_QM_SRF_3 0xE06DCC
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#define mmTPC0_CFG_QM_SRF_4 0xE06DD0
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#define mmTPC0_CFG_QM_SRF_5 0xE06DD4
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#define mmTPC0_CFG_QM_SRF_6 0xE06DD8
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#define mmTPC0_CFG_QM_SRF_7 0xE06DDC
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#define mmTPC0_CFG_QM_SRF_8 0xE06DE0
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#define mmTPC0_CFG_QM_SRF_9 0xE06DE4
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#define mmTPC0_CFG_QM_SRF_10 0xE06DE8
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#define mmTPC0_CFG_QM_SRF_11 0xE06DEC
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#define mmTPC0_CFG_QM_SRF_12 0xE06DF0
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#define mmTPC0_CFG_QM_SRF_13 0xE06DF4
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#define mmTPC0_CFG_QM_SRF_14 0xE06DF8
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#define mmTPC0_CFG_QM_SRF_15 0xE06DFC
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#define mmTPC0_CFG_QM_SRF_16 0xE06E00
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#define mmTPC0_CFG_QM_SRF_17 0xE06E04
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#define mmTPC0_CFG_QM_SRF_18 0xE06E08
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#define mmTPC0_CFG_QM_SRF_19 0xE06E0C
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#define mmTPC0_CFG_QM_SRF_20 0xE06E10
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#define mmTPC0_CFG_QM_SRF_21 0xE06E14
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#define mmTPC0_CFG_QM_SRF_22 0xE06E18
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#define mmTPC0_CFG_QM_SRF_23 0xE06E1C
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#define mmTPC0_CFG_QM_SRF_24 0xE06E20
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#define mmTPC0_CFG_QM_SRF_25 0xE06E24
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#define mmTPC0_CFG_QM_SRF_26 0xE06E28
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#define mmTPC0_CFG_QM_SRF_27 0xE06E2C
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#define mmTPC0_CFG_QM_SRF_28 0xE06E30
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#define mmTPC0_CFG_QM_SRF_29 0xE06E34
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#define mmTPC0_CFG_QM_SRF_30 0xE06E38
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#define mmTPC0_CFG_QM_SRF_31 0xE06E3C
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#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */
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