/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_
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#define ASIC_REG_PSOC_PCI_PLL_REGS_H_
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/*
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*****************************************
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* PSOC_PCI_PLL (Prototype: PLL)
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*****************************************
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*/
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#define mmPSOC_PCI_PLL_NR 0xC72100
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#define mmPSOC_PCI_PLL_NF 0xC72104
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#define mmPSOC_PCI_PLL_OD 0xC72108
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#define mmPSOC_PCI_PLL_NB 0xC7210C
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#define mmPSOC_PCI_PLL_CFG 0xC72110
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#define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120
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#define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128
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#define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C
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#define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130
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#define mmPSOC_PCI_PLL_RST 0xC72134
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#define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150
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#define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200
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#define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204
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#define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208
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#define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C
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#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220
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#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224
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#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228
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#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C
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#define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280
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#define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284
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#define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288
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#define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C
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#define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0
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#define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4
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#define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8
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#define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC
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#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0
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#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4
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#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8
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#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC
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#define mmPSOC_PCI_PLL_CLK_GATER 0xC72300
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#define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310
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#define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314
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#define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318
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#define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C
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#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400
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#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410
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#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420
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#define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430
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#define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440
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#define mmPSOC_PCI_PLL_RLX_BITMAP_CFG 0xC72500
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#define mmPSOC_PCI_PLL_RLX_BITMAP_0 0xC72510
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#define mmPSOC_PCI_PLL_RLX_BITMAP_1 0xC72514
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#define mmPSOC_PCI_PLL_RLX_BITMAP_2 0xC72518
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#define mmPSOC_PCI_PLL_RLX_BITMAP_3 0xC7251C
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#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */
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