/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_PSOC_HBM_PLL_REGS_H_
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#define ASIC_REG_PSOC_HBM_PLL_REGS_H_
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/*
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*****************************************
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* PSOC_HBM_PLL (Prototype: PLL)
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*****************************************
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*/
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#define mmPSOC_HBM_PLL_NR 0xC74100
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#define mmPSOC_HBM_PLL_NF 0xC74104
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#define mmPSOC_HBM_PLL_OD 0xC74108
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#define mmPSOC_HBM_PLL_NB 0xC7410C
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#define mmPSOC_HBM_PLL_CFG 0xC74110
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#define mmPSOC_HBM_PLL_LOSE_MASK 0xC74120
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#define mmPSOC_HBM_PLL_LOCK_INTR 0xC74128
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#define mmPSOC_HBM_PLL_LOCK_BYPASS 0xC7412C
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#define mmPSOC_HBM_PLL_DATA_CHNG 0xC74130
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#define mmPSOC_HBM_PLL_RST 0xC74134
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#define mmPSOC_HBM_PLL_SLIP_WD_CNTR 0xC74150
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#define mmPSOC_HBM_PLL_DIV_FACTOR_0 0xC74200
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#define mmPSOC_HBM_PLL_DIV_FACTOR_1 0xC74204
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#define mmPSOC_HBM_PLL_DIV_FACTOR_2 0xC74208
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#define mmPSOC_HBM_PLL_DIV_FACTOR_3 0xC7420C
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#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_0 0xC74220
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#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_1 0xC74224
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#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_2 0xC74228
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#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_3 0xC7422C
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#define mmPSOC_HBM_PLL_DIV_SEL_0 0xC74280
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#define mmPSOC_HBM_PLL_DIV_SEL_1 0xC74284
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#define mmPSOC_HBM_PLL_DIV_SEL_2 0xC74288
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#define mmPSOC_HBM_PLL_DIV_SEL_3 0xC7428C
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#define mmPSOC_HBM_PLL_DIV_EN_0 0xC742A0
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#define mmPSOC_HBM_PLL_DIV_EN_1 0xC742A4
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#define mmPSOC_HBM_PLL_DIV_EN_2 0xC742A8
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#define mmPSOC_HBM_PLL_DIV_EN_3 0xC742AC
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#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_0 0xC742C0
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#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_1 0xC742C4
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#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_2 0xC742C8
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#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_3 0xC742CC
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#define mmPSOC_HBM_PLL_CLK_GATER 0xC74300
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#define mmPSOC_HBM_PLL_CLK_RLX_0 0xC74310
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#define mmPSOC_HBM_PLL_CLK_RLX_1 0xC74314
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#define mmPSOC_HBM_PLL_CLK_RLX_2 0xC74318
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#define mmPSOC_HBM_PLL_CLK_RLX_3 0xC7431C
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#define mmPSOC_HBM_PLL_REF_CNTR_PERIOD 0xC74400
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#define mmPSOC_HBM_PLL_REF_LOW_THRESHOLD 0xC74410
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#define mmPSOC_HBM_PLL_REF_HIGH_THRESHOLD 0xC74420
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#define mmPSOC_HBM_PLL_PLL_NOT_STABLE 0xC74430
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#define mmPSOC_HBM_PLL_FREQ_CALC_EN 0xC74440
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#define mmPSOC_HBM_PLL_RLX_BITMAP_CFG 0xC74500
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#define mmPSOC_HBM_PLL_RLX_BITMAP_0 0xC74510
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#define mmPSOC_HBM_PLL_RLX_BITMAP_1 0xC74514
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#define mmPSOC_HBM_PLL_RLX_BITMAP_2 0xC74518
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#define mmPSOC_HBM_PLL_RLX_BITMAP_3 0xC7451C
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#endif /* ASIC_REG_PSOC_HBM_PLL_REGS_H_ */
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