/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MMU_UP_REGS_H_
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#define ASIC_REG_MMU_UP_REGS_H_
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/*
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*****************************************
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* MMU_UP (Prototype: MMU)
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*****************************************
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*/
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#define mmMMU_UP_MMU_ENABLE 0xC1100C
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#define mmMMU_UP_FORCE_ORDERING 0xC11010
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#define mmMMU_UP_FEATURE_ENABLE 0xC11014
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#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018
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#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C
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#define mmMMU_UP_LOG2_DDR_SIZE 0xC11020
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#define mmMMU_UP_SCRAMBLER 0xC11024
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#define mmMMU_UP_MEM_INIT_BUSY 0xC11028
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#define mmMMU_UP_SPI_MASK 0xC1102C
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#define mmMMU_UP_SPI_CAUSE 0xC11030
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#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034
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#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038
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#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C
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#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040
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#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044
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#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048
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#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C
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#define mmMMU_UP_SPI_CAUSE_CLR 0xC11050
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#define mmMMU_UP_SLICE_CREDIT 0xC11054
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#define mmMMU_UP_PIPE_CREDIT 0xC11058
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#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C
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#define mmMMU_UP_RAZWI_WRITE_ID 0xC11060
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#define mmMMU_UP_RAZWI_READ_VLD 0xC11064
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#define mmMMU_UP_RAZWI_READ_ID 0xC11068
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#define mmMMU_UP_MMU_BYPASS 0xC1106C
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#endif /* ASIC_REG_MMU_UP_REGS_H_ */
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