/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME2_QM_REGS_H_
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#define ASIC_REG_MME2_QM_REGS_H_
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/*
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*****************************************
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* MME2_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmMME2_QM_GLBL_CFG0 0x168000
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#define mmMME2_QM_GLBL_CFG1 0x168004
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#define mmMME2_QM_GLBL_PROT 0x168008
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#define mmMME2_QM_GLBL_ERR_CFG 0x16800C
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#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010
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#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014
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#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018
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#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C
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#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020
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#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024
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#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028
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#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C
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#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030
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#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034
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#define mmMME2_QM_GLBL_STS0 0x168038
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#define mmMME2_QM_GLBL_STS1_0 0x168040
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#define mmMME2_QM_GLBL_STS1_1 0x168044
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#define mmMME2_QM_GLBL_STS1_2 0x168048
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#define mmMME2_QM_GLBL_STS1_3 0x16804C
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#define mmMME2_QM_GLBL_STS1_4 0x168050
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#define mmMME2_QM_GLBL_MSG_EN_0 0x168054
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#define mmMME2_QM_GLBL_MSG_EN_1 0x168058
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#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C
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#define mmMME2_QM_GLBL_MSG_EN_3 0x168060
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#define mmMME2_QM_GLBL_MSG_EN_4 0x168068
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#define mmMME2_QM_PQ_BASE_LO_0 0x168070
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#define mmMME2_QM_PQ_BASE_LO_1 0x168074
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#define mmMME2_QM_PQ_BASE_LO_2 0x168078
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#define mmMME2_QM_PQ_BASE_LO_3 0x16807C
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#define mmMME2_QM_PQ_BASE_HI_0 0x168080
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#define mmMME2_QM_PQ_BASE_HI_1 0x168084
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#define mmMME2_QM_PQ_BASE_HI_2 0x168088
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#define mmMME2_QM_PQ_BASE_HI_3 0x16808C
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#define mmMME2_QM_PQ_SIZE_0 0x168090
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#define mmMME2_QM_PQ_SIZE_1 0x168094
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#define mmMME2_QM_PQ_SIZE_2 0x168098
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#define mmMME2_QM_PQ_SIZE_3 0x16809C
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#define mmMME2_QM_PQ_PI_0 0x1680A0
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#define mmMME2_QM_PQ_PI_1 0x1680A4
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#define mmMME2_QM_PQ_PI_2 0x1680A8
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#define mmMME2_QM_PQ_PI_3 0x1680AC
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#define mmMME2_QM_PQ_CI_0 0x1680B0
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#define mmMME2_QM_PQ_CI_1 0x1680B4
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#define mmMME2_QM_PQ_CI_2 0x1680B8
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#define mmMME2_QM_PQ_CI_3 0x1680BC
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#define mmMME2_QM_PQ_CFG0_0 0x1680C0
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#define mmMME2_QM_PQ_CFG0_1 0x1680C4
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#define mmMME2_QM_PQ_CFG0_2 0x1680C8
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#define mmMME2_QM_PQ_CFG0_3 0x1680CC
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#define mmMME2_QM_PQ_CFG1_0 0x1680D0
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#define mmMME2_QM_PQ_CFG1_1 0x1680D4
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#define mmMME2_QM_PQ_CFG1_2 0x1680D8
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#define mmMME2_QM_PQ_CFG1_3 0x1680DC
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#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0
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#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4
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#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8
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#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC
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#define mmMME2_QM_PQ_STS0_0 0x1680F0
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#define mmMME2_QM_PQ_STS0_1 0x1680F4
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#define mmMME2_QM_PQ_STS0_2 0x1680F8
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#define mmMME2_QM_PQ_STS0_3 0x1680FC
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#define mmMME2_QM_PQ_STS1_0 0x168100
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#define mmMME2_QM_PQ_STS1_1 0x168104
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#define mmMME2_QM_PQ_STS1_2 0x168108
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#define mmMME2_QM_PQ_STS1_3 0x16810C
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#define mmMME2_QM_CQ_CFG0_0 0x168110
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#define mmMME2_QM_CQ_CFG0_1 0x168114
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#define mmMME2_QM_CQ_CFG0_2 0x168118
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#define mmMME2_QM_CQ_CFG0_3 0x16811C
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#define mmMME2_QM_CQ_CFG0_4 0x168120
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#define mmMME2_QM_CQ_CFG1_0 0x168124
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#define mmMME2_QM_CQ_CFG1_1 0x168128
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#define mmMME2_QM_CQ_CFG1_2 0x16812C
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#define mmMME2_QM_CQ_CFG1_3 0x168130
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#define mmMME2_QM_CQ_CFG1_4 0x168134
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#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138
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#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C
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#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140
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#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144
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#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148
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#define mmMME2_QM_CQ_STS0_0 0x16814C
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#define mmMME2_QM_CQ_STS0_1 0x168150
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#define mmMME2_QM_CQ_STS0_2 0x168154
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#define mmMME2_QM_CQ_STS0_3 0x168158
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#define mmMME2_QM_CQ_STS0_4 0x16815C
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#define mmMME2_QM_CQ_STS1_0 0x168160
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#define mmMME2_QM_CQ_STS1_1 0x168164
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#define mmMME2_QM_CQ_STS1_2 0x168168
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#define mmMME2_QM_CQ_STS1_3 0x16816C
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#define mmMME2_QM_CQ_STS1_4 0x168170
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#define mmMME2_QM_CQ_PTR_LO_0 0x168174
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#define mmMME2_QM_CQ_PTR_HI_0 0x168178
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#define mmMME2_QM_CQ_TSIZE_0 0x16817C
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#define mmMME2_QM_CQ_CTL_0 0x168180
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#define mmMME2_QM_CQ_PTR_LO_1 0x168184
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#define mmMME2_QM_CQ_PTR_HI_1 0x168188
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#define mmMME2_QM_CQ_TSIZE_1 0x16818C
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#define mmMME2_QM_CQ_CTL_1 0x168190
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#define mmMME2_QM_CQ_PTR_LO_2 0x168194
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#define mmMME2_QM_CQ_PTR_HI_2 0x168198
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#define mmMME2_QM_CQ_TSIZE_2 0x16819C
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#define mmMME2_QM_CQ_CTL_2 0x1681A0
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#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4
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#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8
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#define mmMME2_QM_CQ_TSIZE_3 0x1681AC
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#define mmMME2_QM_CQ_CTL_3 0x1681B0
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#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4
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#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8
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#define mmMME2_QM_CQ_TSIZE_4 0x1681BC
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#define mmMME2_QM_CQ_CTL_4 0x1681C0
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#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4
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#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8
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#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC
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#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0
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#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4
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#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8
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#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC
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#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0
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#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4
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#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8
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#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC
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#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0
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#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4
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#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8
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#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC
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#define mmMME2_QM_CQ_CTL_STS_0 0x168200
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#define mmMME2_QM_CQ_CTL_STS_1 0x168204
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#define mmMME2_QM_CQ_CTL_STS_2 0x168208
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#define mmMME2_QM_CQ_CTL_STS_3 0x16820C
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#define mmMME2_QM_CQ_CTL_STS_4 0x168210
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#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214
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#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218
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#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C
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#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220
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#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248
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#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270
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#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298
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#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0
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#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4
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#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8
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#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC
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#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0
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#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4
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#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8
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#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0
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#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4
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#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8
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#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC
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#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0
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#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4
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#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8
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#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC
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#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300
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#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304
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#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308
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#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C
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#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310
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#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314
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#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318
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#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C
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#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320
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#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324
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#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328
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#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C
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#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330
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#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334
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#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338
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#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C
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#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340
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#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344
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#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348
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#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C
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#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350
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#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354
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#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358
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#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C
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#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360
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#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364
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#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368
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#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C
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#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370
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#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374
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#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378
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#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C
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#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380
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#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384
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#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388
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#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C
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#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390
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#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394
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#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398
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#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C
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#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0
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#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4
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#define mmMME2_QM_CP_STS_0 0x1683A8
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#define mmMME2_QM_CP_STS_1 0x1683AC
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#define mmMME2_QM_CP_STS_2 0x1683B0
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#define mmMME2_QM_CP_STS_3 0x1683B4
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#define mmMME2_QM_CP_STS_4 0x1683B8
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#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC
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#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0
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#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4
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#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8
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#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC
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#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0
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#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4
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#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8
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#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC
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#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0
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#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4
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#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8
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#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC
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#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400
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#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404
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#define mmMME2_QM_CP_DBG_0_0 0x168408
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#define mmMME2_QM_CP_DBG_0_1 0x16840C
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#define mmMME2_QM_CP_DBG_0_2 0x168410
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#define mmMME2_QM_CP_DBG_0_3 0x168414
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#define mmMME2_QM_CP_DBG_0_4 0x168418
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#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C
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#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420
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#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424
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#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428
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#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C
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#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430
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#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434
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#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438
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#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C
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#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440
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#define mmMME2_QM_ARB_CFG_0 0x168A00
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#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04
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#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08
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#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C
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#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10
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#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14
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#define mmMME2_QM_ARB_CFG_1 0x168A18
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98
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#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C
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#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C
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#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20
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#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28
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#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C
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#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34
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#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38
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#define mmMME2_QM_ARB_SLV_ID 0x168B3C
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#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44
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#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48
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#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C
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#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50
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#define mmMME2_QM_ARB_BASE_LO 0x168B54
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#define mmMME2_QM_ARB_BASE_HI 0x168B58
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#define mmMME2_QM_ARB_STATE_STS 0x168B80
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#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84
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#define mmMME2_QM_ARB_MSG_STS 0x168B88
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#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C
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#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C
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#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0
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#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8
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#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0
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#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4
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#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8
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#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC
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#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0
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#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4
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#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8
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#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC
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#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0
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#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4
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#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8
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#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC
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#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0
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#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4
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#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8
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#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC
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#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0
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#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4
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#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8
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#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC
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#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00
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#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04
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#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08
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#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C
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#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10
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#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14
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#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18
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#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C
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#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20
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#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24
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#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28
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#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C
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#define mmMME2_QM_CGM_CFG 0x168C70
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#define mmMME2_QM_CGM_STS 0x168C74
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#define mmMME2_QM_CGM_CFG1 0x168C78
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#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80
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#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84
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#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90
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#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94
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#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98
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#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C
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#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0
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#define mmMME2_QM_GLBL_AXCACHE 0x168CA4
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#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0
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#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4
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#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8
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#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC
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#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0
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#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4
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#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8
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#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00
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#endif /* ASIC_REG_MME2_QM_REGS_H_ */
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