/* SPDX-License-Identifier: GPL-2.0
|
*
|
* Copyright 2016-2018 HabanaLabs, Ltd.
|
* All Rights Reserved.
|
*
|
*/
|
|
/************************************
|
** This is an auto-generated file **
|
** DO NOT EDIT BELOW **
|
************************************/
|
|
#ifndef ASIC_REG_DMA7_QM_REGS_H_
|
#define ASIC_REG_DMA7_QM_REGS_H_
|
|
/*
|
*****************************************
|
* DMA7_QM (Prototype: QMAN)
|
*****************************************
|
*/
|
|
#define mmDMA7_QM_GLBL_CFG0 0x5E8000
|
|
#define mmDMA7_QM_GLBL_CFG1 0x5E8004
|
|
#define mmDMA7_QM_GLBL_PROT 0x5E8008
|
|
#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C
|
|
#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010
|
|
#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014
|
|
#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018
|
|
#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C
|
|
#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020
|
|
#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024
|
|
#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028
|
|
#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C
|
|
#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030
|
|
#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034
|
|
#define mmDMA7_QM_GLBL_STS0 0x5E8038
|
|
#define mmDMA7_QM_GLBL_STS1_0 0x5E8040
|
|
#define mmDMA7_QM_GLBL_STS1_1 0x5E8044
|
|
#define mmDMA7_QM_GLBL_STS1_2 0x5E8048
|
|
#define mmDMA7_QM_GLBL_STS1_3 0x5E804C
|
|
#define mmDMA7_QM_GLBL_STS1_4 0x5E8050
|
|
#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054
|
|
#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058
|
|
#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C
|
|
#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060
|
|
#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068
|
|
#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070
|
|
#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074
|
|
#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078
|
|
#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C
|
|
#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080
|
|
#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084
|
|
#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088
|
|
#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C
|
|
#define mmDMA7_QM_PQ_SIZE_0 0x5E8090
|
|
#define mmDMA7_QM_PQ_SIZE_1 0x5E8094
|
|
#define mmDMA7_QM_PQ_SIZE_2 0x5E8098
|
|
#define mmDMA7_QM_PQ_SIZE_3 0x5E809C
|
|
#define mmDMA7_QM_PQ_PI_0 0x5E80A0
|
|
#define mmDMA7_QM_PQ_PI_1 0x5E80A4
|
|
#define mmDMA7_QM_PQ_PI_2 0x5E80A8
|
|
#define mmDMA7_QM_PQ_PI_3 0x5E80AC
|
|
#define mmDMA7_QM_PQ_CI_0 0x5E80B0
|
|
#define mmDMA7_QM_PQ_CI_1 0x5E80B4
|
|
#define mmDMA7_QM_PQ_CI_2 0x5E80B8
|
|
#define mmDMA7_QM_PQ_CI_3 0x5E80BC
|
|
#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0
|
|
#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4
|
|
#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8
|
|
#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC
|
|
#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0
|
|
#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4
|
|
#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8
|
|
#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC
|
|
#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0
|
|
#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4
|
|
#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8
|
|
#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC
|
|
#define mmDMA7_QM_PQ_STS0_0 0x5E80F0
|
|
#define mmDMA7_QM_PQ_STS0_1 0x5E80F4
|
|
#define mmDMA7_QM_PQ_STS0_2 0x5E80F8
|
|
#define mmDMA7_QM_PQ_STS0_3 0x5E80FC
|
|
#define mmDMA7_QM_PQ_STS1_0 0x5E8100
|
|
#define mmDMA7_QM_PQ_STS1_1 0x5E8104
|
|
#define mmDMA7_QM_PQ_STS1_2 0x5E8108
|
|
#define mmDMA7_QM_PQ_STS1_3 0x5E810C
|
|
#define mmDMA7_QM_CQ_CFG0_0 0x5E8110
|
|
#define mmDMA7_QM_CQ_CFG0_1 0x5E8114
|
|
#define mmDMA7_QM_CQ_CFG0_2 0x5E8118
|
|
#define mmDMA7_QM_CQ_CFG0_3 0x5E811C
|
|
#define mmDMA7_QM_CQ_CFG0_4 0x5E8120
|
|
#define mmDMA7_QM_CQ_CFG1_0 0x5E8124
|
|
#define mmDMA7_QM_CQ_CFG1_1 0x5E8128
|
|
#define mmDMA7_QM_CQ_CFG1_2 0x5E812C
|
|
#define mmDMA7_QM_CQ_CFG1_3 0x5E8130
|
|
#define mmDMA7_QM_CQ_CFG1_4 0x5E8134
|
|
#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138
|
|
#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C
|
|
#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140
|
|
#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144
|
|
#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148
|
|
#define mmDMA7_QM_CQ_STS0_0 0x5E814C
|
|
#define mmDMA7_QM_CQ_STS0_1 0x5E8150
|
|
#define mmDMA7_QM_CQ_STS0_2 0x5E8154
|
|
#define mmDMA7_QM_CQ_STS0_3 0x5E8158
|
|
#define mmDMA7_QM_CQ_STS0_4 0x5E815C
|
|
#define mmDMA7_QM_CQ_STS1_0 0x5E8160
|
|
#define mmDMA7_QM_CQ_STS1_1 0x5E8164
|
|
#define mmDMA7_QM_CQ_STS1_2 0x5E8168
|
|
#define mmDMA7_QM_CQ_STS1_3 0x5E816C
|
|
#define mmDMA7_QM_CQ_STS1_4 0x5E8170
|
|
#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174
|
|
#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178
|
|
#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C
|
|
#define mmDMA7_QM_CQ_CTL_0 0x5E8180
|
|
#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184
|
|
#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188
|
|
#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C
|
|
#define mmDMA7_QM_CQ_CTL_1 0x5E8190
|
|
#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194
|
|
#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198
|
|
#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C
|
|
#define mmDMA7_QM_CQ_CTL_2 0x5E81A0
|
|
#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4
|
|
#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8
|
|
#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC
|
|
#define mmDMA7_QM_CQ_CTL_3 0x5E81B0
|
|
#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4
|
|
#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8
|
|
#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC
|
|
#define mmDMA7_QM_CQ_CTL_4 0x5E81C0
|
|
#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4
|
|
#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8
|
|
#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC
|
|
#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0
|
|
#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4
|
|
#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8
|
|
#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC
|
|
#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0
|
|
#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4
|
|
#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8
|
|
#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC
|
|
#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0
|
|
#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4
|
|
#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8
|
|
#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC
|
|
#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200
|
|
#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204
|
|
#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208
|
|
#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C
|
|
#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210
|
|
#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214
|
|
#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218
|
|
#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C
|
|
#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220
|
|
#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248
|
|
#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270
|
|
#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298
|
|
#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0
|
|
#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4
|
|
#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8
|
|
#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC
|
|
#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0
|
|
#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4
|
|
#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8
|
|
#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0
|
|
#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4
|
|
#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8
|
|
#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC
|
|
#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0
|
|
#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4
|
|
#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8
|
|
#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC
|
|
#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300
|
|
#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304
|
|
#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308
|
|
#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C
|
|
#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310
|
|
#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314
|
|
#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318
|
|
#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C
|
|
#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320
|
|
#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324
|
|
#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328
|
|
#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C
|
|
#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330
|
|
#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334
|
|
#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338
|
|
#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C
|
|
#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340
|
|
#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344
|
|
#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348
|
|
#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C
|
|
#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350
|
|
#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354
|
|
#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358
|
|
#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C
|
|
#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360
|
|
#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364
|
|
#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368
|
|
#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C
|
|
#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370
|
|
#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374
|
|
#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378
|
|
#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C
|
|
#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380
|
|
#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384
|
|
#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388
|
|
#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C
|
|
#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390
|
|
#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394
|
|
#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398
|
|
#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C
|
|
#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0
|
|
#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4
|
|
#define mmDMA7_QM_CP_STS_0 0x5E83A8
|
|
#define mmDMA7_QM_CP_STS_1 0x5E83AC
|
|
#define mmDMA7_QM_CP_STS_2 0x5E83B0
|
|
#define mmDMA7_QM_CP_STS_3 0x5E83B4
|
|
#define mmDMA7_QM_CP_STS_4 0x5E83B8
|
|
#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC
|
|
#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0
|
|
#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4
|
|
#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8
|
|
#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC
|
|
#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0
|
|
#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4
|
|
#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8
|
|
#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC
|
|
#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0
|
|
#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4
|
|
#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8
|
|
#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC
|
|
#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400
|
|
#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404
|
|
#define mmDMA7_QM_CP_DBG_0_0 0x5E8408
|
|
#define mmDMA7_QM_CP_DBG_0_1 0x5E840C
|
|
#define mmDMA7_QM_CP_DBG_0_2 0x5E8410
|
|
#define mmDMA7_QM_CP_DBG_0_3 0x5E8414
|
|
#define mmDMA7_QM_CP_DBG_0_4 0x5E8418
|
|
#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C
|
|
#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420
|
|
#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424
|
|
#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428
|
|
#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C
|
|
#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430
|
|
#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434
|
|
#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438
|
|
#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C
|
|
#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440
|
|
#define mmDMA7_QM_ARB_CFG_0 0x5E8A00
|
|
#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04
|
|
#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08
|
|
#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C
|
|
#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10
|
|
#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14
|
|
#define mmDMA7_QM_ARB_CFG_1 0x5E8A18
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98
|
|
#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C
|
|
#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C
|
|
#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20
|
|
#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28
|
|
#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C
|
|
#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34
|
|
#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38
|
|
#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C
|
|
#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44
|
|
#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48
|
|
#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C
|
|
#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50
|
|
#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54
|
|
#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58
|
|
#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80
|
|
#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84
|
|
#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88
|
|
#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C
|
|
#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C
|
|
#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0
|
|
#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28
|
|
#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C
|
|
#define mmDMA7_QM_CGM_CFG 0x5E8C70
|
|
#define mmDMA7_QM_CGM_STS 0x5E8C74
|
|
#define mmDMA7_QM_CGM_CFG1 0x5E8C78
|
|
#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80
|
|
#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84
|
|
#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90
|
|
#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94
|
|
#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98
|
|
#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C
|
|
#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0
|
|
#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4
|
|
#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0
|
|
#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4
|
|
#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8
|
|
#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC
|
|
#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0
|
|
#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4
|
|
#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8
|
|
#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00
|
|
#endif /* ASIC_REG_DMA7_QM_REGS_H_ */
|
